14nm FinFET

300mm wafers with 14nm Bulk FinFET devices

  • Silicon EPI nFET/pFET CMOS fully integrated vehicle
  • Embedded Si:P / SigGe S/D CMOS fully integrated vehicle
  • Replacement Metal Gate [RMG] with Local Interconnect
  • Single level BEOL metal

14nm Bulk finFET devices

#Digital and #Analog/RF existing test chips

  • Complete suite of #test structures for #Reliability/ESD/Local Layout effects/…
  • Standard devices up to circuit level [Ring-Oscillators, …]
  • State-of-the-art #bulk #FinFET device baseline
  • #Documentation of process assumptions for the test chips
  • Access to test structures #data


  • >500m2 of test labs, ~25 semiauto/manual 300mm probers
  • Statistical data treatment in JMP
  • Fully and Semi-automatic 300mm parametric testers
  • Temperature range for test on wafers 77/10K to high T
  • Fast Pulse testing, Self-Heating characterization
  • HF tests up to 50GHz
  • Noise measurements
  • Reliability tests: hot carriers, TDDB, charge pumping, …
  • High power tests (10kV, >100A) on 300mm prober
  • Electrostatic discharge LAB

Ascent+ facility

Platform Technology

  • Disruptive Devices

Key Enabling Capabilities

  • Devices / Test structures
  • Modelling / Databases
  • Processing [Module]
  • Characterisation: Electrical

Case Study

Access, as offered in ASCENT, first part of the project either granted access to existing silicon, ready for user to perform tests or get electrical data from imec; this included noise, matching/variability, …

Silicon processing, although not out of scope, has to be limited to small number of steps, which in ASCENT resulted in samples being prepared with full BEOL passivation ready to be bonded for performing tests at package level.

[DOI: 10.1109/EDTM47692.2020.9117815]
[DOI: 10.1109/EDTM.2019.8731200]
[DOI: 10.1109/ICMTS.2017.7954263]

Key Enabling Capability

Devices / Test Structures, Metrology / Characterisation, Modelling / Databases, Processing

Platform Technology

Disruptive Devices