Success Stories – ASCENT+

ASCENT+ Access Project: Electrical Characterisation of Advanced SOI MOSFETs (RefNo 384)
User: Michelly de Souza
Affiliation: Centro Universitario FEI, Sao Bernardo do Campo, Brazil
Problem: FD SOI transistors have been considered for 3D integration, allowing for increased circuit density. The analysis of the temperature influence on the operation of electronic devices is of great importance, as temperature variations cause significant changes in their electrical behaviour, which may impair or improve the performance of ICs. The operation of MOSFETs at low temperatures offers performance improvement in relation to the operation at room temperature, and is of great importance in applications such as aerospace and, more recently, for interfacing circuits between qubits and CMOS logic in quantum computing. Therefore we need to investigate the electrical performance of state-of-the-art FD SOI MOSFETs when exposed to extreme temperature conditions through experimental electrical measurements.
Solution: Perform electrical characterisation of advanced SOI CMOS transistors at different temperatures of operation. The effect of temperature reduction will be evaluated by means of the analysis of electrical parameters extracted from the experimental measurements. Obtain experimental electrical characteristics of FD SOI CMOS transistors at room and cryogenic temperatures. Perform analysis of carrier transport in stacked FD SOI aiming at 3D integration. In stacked FD SOI MOSFETs, fabricated at different thermal conditions, the effect of temperature of operation over the mobility at different levels was evaluated.
Results: During the visit to CEA-Leti, we conducted electrical characterisation of advanced SOI CMOS transistors at various operating temperatures. Measurements were performed on transistors designed for 3D integration, fabricated at low temperatures, as well as on 7-level stacked nanosheet transistors. The resulting data enables analysis of carrier transport in these transistors, highlighting diverse approaches to enhancing integration density in integrated circuits. In addition to advancing the understanding of the physics behind these cutting-edge transistors, the experimental analysis of their electrical characteristics will facilitate the refinement of numerical simulation and analytical models to accurately describe observed temperature-dependent effects.
Testimonial: “The ASCENT+ program strengthened the long-term collaboration between researchers from CEA-Leti and FEI University. Visiting the CEA-Leti laboratories and having in-person interactions with the involved researchers were truly unique experiences. The resulting data is enabling the analysis of carrier transport in cutting-edge transistors, meant to enhance integration density in integrated circuits. Apart from advancing our understanding of the underlying physics of these devices, the obtained experimental data will aid the refinement of numerical simulations and analytical models to represent temperature-dependent effects accurately. I would like to express my gratitude to all the researchers and staff in CEA-Leti’s Silicon Components Department for their welcoming reception, excellent support, and fruitful discussions.”

ASCENT+ Access Project: 2D materials interface with 2D and 3D materials (RefNo 377)
User: Kimberly Intonti
Affiliation: Electronic Nanodevices group, University of Salerno, Fisciano, Italy
Problem: Integration of 2D materials with 3D semiconductors can provide an excellent platform to study light interaction and electric transport at the interface, which could be exploited to develop, among others, new broadband photodetectors. Additionally, new electronic properties would emerge by combining different functional 2D materials, so it is necessary to study the properties of their interfaces.
Solution: Rhenium disulfide (ReS₂) is an attractive option for photodetection both for direct bandgap enhanced photogeneration and the potential to use thicker flakes for higher light absorption. Therefore, large area 2D ReS₂ flakes were mechanically exfoliated and subsequently transferred onto a low doped n-type Si substrate, obtaining a type II 2D/3D heterostructure. The devices were manufactured at the ASCENT+ Access Provider. Then, at the University of Salerno, a supercontinuum white laser coupled with a nano-positioned optical fibre was used to study their photo-response under local illumination.
Results: ReS₂/Si 2D/3D heterostructures for efficient photodetection were successfully fabricated. In the dark, the heterojunction exhibits diode-like behaviour with low reverse current and a high rectification ratio. The photocurrent rises linearly with light intensity at every bias, and the photo-switching behaviour shows a stable and repeatable response. The device can also operate in photovoltaic mode with a response time of less than one millisecond. Additionally, DFT simulations helped to better understand the transport mechanisms at the ReS₂/Si interface. These promising findings pave the way for the realisation of ReS₂/Si-based photodiodes for broadband and high-speed photodetection applications.
Testimonial: “I’m a PhD student in Physics and emerging technologies at the University of Salerno (Italy). My research project focuses on the electrical and optical characterisation of 2D material-based nanodevices. Through ASCENT+, I had the possibility to access the laboratories of Tyndall National Institute and collaborate with an excellent group of professionals who helped me in the realisation of ReS₂/Si heterostructures for efficient photodetection. Exciting experimental results from the study project, accompanied by the DFT simulation provided by the hosting group, are suitable for publishing and will be helpful for my PhD project. Thanks to ASCENT+ covering all of my costs, I was able to benefit from this opportunity for free. All PhD candidates who wish to work with other institutions and gain new research skills should definitely take advantage of this experience!”

ASCENT+ Access Project: XPS/SEM study of titanium based alloy powders (RefNo 375)
User: Dmytro Savvakin
Affiliation: Institute for Metal Physics (IMP), NAS of Ukraine, Kyiv, Ukraine
Problem: We are currently developing powder metallurgy technologies to create titanium-based materials with improved characteristics. The surface condition of metallic powders, including their phase and chemical composition, presence of surface oxide layers and absorbed impurities is extremely important for physical properties and chemical activity of powders. Moreover, noted surface characteristics of powders affect their sintering ability and characteristics of final product obtained with powder metallurgy technologies.
Solution: We need help with the comparative investigation of absorbed impurities, surface and sub-surface nano-structured oxide layers at titanium Ti-Al-Cr-Nb alloy and corresponding hydrogenated alloy powders. The surface characteristics of titanium-based powders were studied using XPS, XPS Ar ion beam depth profiling and SEM methods to develop approaches for powder cleaning and sintering activation.
Results: The access provided was successfully completed providing important data about surface structure and surface oxide layers at titanium Ti-Al-Cr-Nb alloy and corresponding hydrogenated alloy powders.
Testimonial: “I would like to express my sincere gratitude to the ASCENT+ program for the opportunity to obtain new and important experimental data using modern equipment. New experimental data about surface structure at titanium Ti-Al-Cr-Nb alloy and corresponding hydrogenated alloy powders were obtained. Data will contribute to development of powder metallurgy technologies and improvement of characteristics of titanium-based products.”

ASCENT+ Access Project: Study of active ingredients in polymer composites (RefNo 358)
User: Sylwia Kozdra
Affiliation: Institute of Microelectronics and Photonics, Łukasiewicz Research Network Warsaw, Poland
Problem: We are currently developing polymer composites with the addition of alkali metals salts. During preliminary studies, significant differences appear in composites properties, especially electrical characteristics. Conductivity is crucial for the functionality of materials used as solid polymer electrolytes (SPE). We need to characterise the composition of the polymer composites and use this information to find a correlation between the composition and properties of SPEs produced by different techniques.
Solution: Using the ToF SIMS technique allow us to characterise the composition of the polymer composites with the addiction of alkali metals salts. In particular, the composition of the composite near the surface is crucial. The ToF SIMS technique is suitable for the study of organic materials and is expected to provide information on the composition of the produced composites, taking into account the surface.
Results: The main aim of the ToF-SIMS study of a series of polymer composite samples with various variants of active additives: LiClO₄, NaClO₄ and inert ones (SiO₂ and TiO2) was to determine the impact of the composite composition on the distribution of individual components, especially lithium and sodium salts. The research results were presented in the form of depth profiles originating from positively charged structures. During the analysis, individual fragments can be assigned to the components of the composites and their distribution and intensity on the surface and in the sample mass can be compared. ToF SIMS tests were performed for several samples of polymer composites and positive profiles were obtained for the structures corresponding to the individual components. However, differences in the height of individual signals were noticed depending on the composition and technique of sample preparation. Combining the information provided by ToF-SIMS with the results of other characterisation techniques will provide a better understanding of the polymer composites.
Testimonial: “It can be seen that PVDF composites with the addition of PMMA show more uniform profiles than those without PMMA. Improved uniformity results in faster flattening of profiles, which means a thinner, non-uniform layer on the surface. Greater heterogeneity after SBS does not positively affect the distribution of LiClO₄ and increases the charging effect/unevenness. We observe different effects on samples with the addition of LiClO₄ and NaClO₄, which means that the inert additives, SiO₂ and TiO₂, have a different effect on lithium and sodium ions in the polymer matrix. The obtained results provide valuable information on the interaction of alkali metals on the matrix of polymer composites processed by various techniques.”

ASCENT+ Access Project: Process development for molecular electronics (RefNo 319)
User: Roberto Guarino
Affiliation: Koral Technologies Srl, Trento, Italy
Problem: Molecular Electronics (ME) consists in the realisation of electronic components through single molecules or small packets of molecules. It was born as a promising answer to the intrinsic limits of scaling in the ICT field. ME has recently gained new popularity thanks to its successful demonstration in ultra-sensitive single-molecule sensors. We have developed Au-based nano-structures to address the study both of devices for computing applications and of single-molecule nano-sensors, but with lack the required nanofabrication facilities.
Solution: We will deposit a thin Au layer and then realise nano-patterning by means of electron beam lithography. We aim to develop a fabrication process capable of reaching the resolution of interest, i.e. 10nm or less for the smallest features. The access, therefore, focused on the development and optimisation of a suitable wafer processing method for reaching the desired resolution together with a reasonable yield.
Results: Electron beam lithography and ion milling at INL, Portugal, were used to generate nanometer-sized Au electrodes on commercial Si wafers. The objectives were challenging and, despite not all of them were achieved, we were able to test the limitations of the available infrastructure and we have put the basis for future work./dd>
Access provided: Access to nanofabrication at INL.
Testimonial: “The ASCENT+ network supported us with a Transnational Access that was a great opportunity to verify our preliminary designs and boost our experimental activities. The experience and expertise of INL was fundamental to achieve the planned objectives and to make the project successful. Furthermore, it allowed us to plan future experimental steps, also within a subsequent ASCENT+ Access.”

ASCENT+ Access Project: FeCAP stack patterning and structural characterisation (RefNos 317 and 344)
User: Stefan Müller
Affiliation: Ferroelectric Memory Company, Dresden, Germany
Problem: FMC has developed a novel ferroelectric capacitor (FeCAP) based memory technology that has the potential for use in a wide range of embedded and standalone memory applications. Within this TA project, Ferroelectric Memory GmbH (FMC) wanted to evaluate if its ferroelectric capacitor stack technology could be etched into small capacitors structures (200nm in diameter).
Solution: First we had to establish a wafer exchange protocol to bring our external wafers into CEA-Leti. In a second phase the wafers were patterned and analysed by structural characterisation (SEM, TEM, etc.).
Results: The first phase successfully developed a wafer exchange protocol for bringing external wafers from FMC into CEA-Leti. This included the verification of appropriate defect levels via ICP-MS / TXR analysis. In the second phase, FeCAP stacks provided by FMC were successfully patterned and analysed by structural characterisation. Based on these results the best stack architecture was selected for further development work on ferroelectric memory technology.
Testimonial: “A wafer exchange protocol was successfully established that allows for insertion of externally processed wafers into Leti facilities for further fabrication. The protocol consists of an ICP-MS and a TXRF analysis. Ferroelectric capacitor stacks were successfully patterned by reactive ion etching using a one step lithography process. Profiles of ferroelectric stacks were judged to be suitable for integration into ferroelectric capacitor process flow.”

ASCENT+ Access Project: Purified Silicon EpiTest (RefNo 305)
Users: Brendan Barry and Amir Sammak
Affiliation: Equal1, Dublin, Ireland
Problem: Regular silicon wafers consist of ~95% Si₂₈ isotope, and ~5% Si₂₉ isotope. When the wafer is used as a quantum processor with spin electrons trapped in a quantum dot (transistor well) the Si₂₉ isotope damages the spin electron qubit, causing it to degrade 10-100× faster. The usefulness of a qubit is a function of the length of time it survives in quantum state before degrading to classical state. However, purified silicon (99.97% Si₂₈ isotope), is difficult and expensive to produce.
Solution: Applying a thin layer of purified silicon epitaxy (order of 100nm) the spin qubits are isolated from impurities, their lifespan is improved 10-100× longer, exceeding the usefulness threshold allowing them to be applied to implement quantum algorithms. Developing the mechanism to apply purified silicon (isotope 28) epitaxy to a 300mm wafer to enable next generation high quality spin qubits for quantum processor development.
Results: Fraunhofer IPMS did a series of natural and isotopically purified silicon epitaxy in a 300 mm high-volume reactor. For this, a multi-wafer epitaxy reactor was equipped with an isotopically purified silicon precursor and tuned with precise process-control and consistency. All material specifications were met as planned, with quality that exceeds the requirement for proposed high-fidelity spin-qubits.
Testimonial: “This collaboration was aimed to create milestones in material development for silicon-based quantum devices. The numerous material characterizations generated in this project have enabled growth and analysis of isotopically purified silicon in various schemes for state-of-the-art fabrication of high-fidelity spin-qubits. Moreover, this program has formed a special way-of-work that binds multiple European entities in the pursuit of material quality for quantum applications.”

ASCENT+ Access Project: Nanoscale domain analysis of Pb-free relaxors (RefNo 296)
User: T Wesley Surta
Affiliation: Department of Physics & Stephenson Institute for Renewable Energy, University of Liverpool, United Kingdom
Problem: We have discovered a new system of Pb-free relaxors which show promising piezoelectric and ferroelectric properties. Relaxors have nano-scale domains of polarization which dictate their physical response and presents a new design strategy for piezoelectrics. To fully understand the mechanisms which yields the enhanced piezoelectric response observed it is vital to understand the sizes and structures of the polar nano domains. The nano-scale nature of piezo-response force microscopy (PFM) lends itself perfectly to this task, revealing the shape, size, and spatial distribution of domain features.
Solution: The observation of the domain structure through this compositional region by PFM gives insights into the influence the nanoscale structural features have on the bulk properties. Additionally, we measured local strain and polarization on the surface of these ceramics to complement the properties observed in the bulk.
Results/Outputs: This work helped contextualise our new piezoelectric materials relative to known ones. It also helped understand our single crystal growth experiments and how the domain structure changes between polycrystalline and single crystal samples.
DOI: 10.1016/j.actamat.2023.119594 – T.W. Surta et al., “Separation of K⁺ and Bi³⁺ displacements in a Pb-free, monoclinic piezoelectric at the morphotropic phase boundary”, Acta Materialia, 119594 (Dec 2023)
Testimonial: “The ASCENT+ programme gave our research team access to vital tools for developing a comprehensive view of our new piezoelectric materials. This information helped our team understand the structure of the material and therefore the mechanism which underpinned the physical response. With this information we have been able to not only understand the materials, but also target methods for improvement and design of the next generation of Pb-free piezoelectrics.”

ASCENT+ Access Project: Photonic PDMS-based sensors for IBD detection (RefNo 294)
User: Sara Daniela Teixeira Resende
Affiliation: Instituto Superior Técnico, Lisbon University, Portugal
Problem: We were developing a photonic-based sensor on a nanoscale patterned polydimethylsiloxane (PDMS) structure acting as transducer, combined with a molecularly imprinted polymer for fast and sensitive detection of calprotectin, a biomarker for inflammatory bowel diseases (IBD). The sensor structure was prepared by nanoimprint lithography with a specific photonic pattern on a silicon wafer and replicating the same pattern into PDMS. The unique grating design provided PDMS photonic properties, suitable to be used as sensing layer. The polymer deposited in the trenches of the grating acts as the biorecognition element, and is key to achieve a sensitive detection of the target biomarker. We wanted to understand where in the grating the polymer is deposited (on the bottom of the trenches, on the top or on the side walls).
Solution: Characterisation of innovative sensor supports – perform topographic analysis of PDMS with grating and PDMS with grating and polymer using AFM and nanoindenter.
Results: Clear difference between the PDMS with grating and the PDMS with grating and polymer. The topographic images showed an accumulation of the polymer on the top parts, as expected. However, even with a more appropriate tip it was not possible to measure the entire height or to see if the polymer was deposited on the trenches, since forcing the tip to go any lower would damage it.
Testimonial: “I was given the opportunity to visit the Fraunhofer IZM in the beautiful city of Dresden! I learnt a lot more about Atomic Force Microscopy and analysed the substrates that I used for the construction of my photonic sensors. It was a great experience and everyone at Fraunhofer received me very well. I also did a presentation of my PhD work for all the people that were interested in learning more about photonic sensors and research in academia. I would like to express my gratitude to Laura Wenzel, whose valuable expertise in this technique made the analysis easier; and another huge thanks to Thomas Werner, for receiving me so well and taking care of all the details for this trip. It was a pleasure to be in this facility, meet all the amazing researchers and engineers, have a cleanroom tour and talk a little bit about my PhD work!”

Video Testimonial

*Pocket wafer with inserted Pillar Hall Chips*

ASCENT+ Access Project

300mm Test Wafer Process (RefNo 282)

User

Mikko Utriainen

Affiliation

Chipmetrics Oy, Joensuu, Finland

Problem

Chipmetrics is a developer and supplier of special metrology chips for ALD, CVD and related thin film process development and monitoring. Our main product – PillarHall™ Lateral High Aspect Ratio (LHAR) test chip and measurement method for thin-film process conformality characterisation, is developed to accelerate applications of conformal 3D thin films in high aspect ratio challenges. PillarHall™ metrology chips are currently manufactured on ∅150mm wafers using MEMS processes, and eventually delivered to customers as a singulated die. Since most leading-edge industrial technologies are currently using ∅300mm wafers, a solution was needed to scale the PillarHall™ technology to larger wafer sizes.

Solution

After internal review, Fraunhofer IZM-ASSID in Dresden was assigned as our partner to develop a pocket wafer approach and related technical solution for this challenge. At the beginning of the project, a set of requirements was defined:

Wafer size: ∅300mm
Chip size for the etched pockets: 15×15mm
Number of pockets on wafer: 9
Depth of pockets: <500µm
Sufficient adhesion of chips on pockets to allow shipping of wafers
Compatibility with vacuum processing (low outgassing)
Temperature tolerance: >400°C

Within the project, pocket wafers were manufactured using a plasma etch method. While the plasma etching of pockets is an established process, the challenge was to find a suitable adhesive material and bonding process to fulfil the requirements. Several DOE runs were performed to investigate various adhesive materials and related curing and annealing processes.

Results

Within this work, a liquid glass type material was found which offered superior adhesion. Furthermore, stability of the bonded chips was demonstrated up to 550°C. An initial test showed only minor outgassing, however more work is required to deliver a final assessment of the vacuum-processing compatibility of this approach.

Access provided: Access to 3D system development and prototyping at Fraunhofer IZM-ASSID.

Testimonial

“As Chipmetrics we were very impressed with the vast resources offered by the ASCENT+ network. The work at Fraunhofer IZM-ASSID was performed with great professionalism and dedication. As a result, we are now able to provide the first samples of ∅300mm pocket wafers with attached PillarHall™ LHAR4 test chips. These samples and the related technology developed within this project will be essential to develop forward the PillarHall™ LHAR pocket wafer and measurement method for a real industrial semiconductor process monitoring applications.”

ASCENT+ Access Project: Deposition of tantalum nitride thin film resistors (RefNo 258)
User: Valeriy Shunkov
Affiliation: POLYN Technology, London, United Kingdom
Problem: The AI world has been looking for a technology that allows neural networks to work off-line while consistently performing with high accuracy, under very little power, with the ability to read data directly from analog sensors, and that is cost effective.
Solution: Semiconductor grade deposited ultrathin TaN on wafer level is a suitable candidate as a robust high-resistance layer for resistors.
Testimonial: “The joint project of Fraunhofer Mikroelektronik and POLYN Technology to develop a special process as one of the elements of next-generation POLYN’s Neuromorphic Analog Signal Processor (NASP) was successfully completed. ASCENT+ provided POLYN with a unique opportunity to utilise Fraunhofer IPMS’ expertise in microelectronics. We look forward to continuing our collaboration.”

*GaN-Royer IC with power and control transistors*

ASCENT+ Access Project: Self-Oscillating Resonance Power Converter (RefNo 254)
User: Manuel Rueß
Affiliation: Institute of Robust Power Semiconductor Systems (ILH), University of Stuttgart, Germany
Problem: A self-oscillating transistor circuit is used as the fundamental element for a resonant power converter for wireless power transmission (WPT) applications. Within the current state of the art for such circuits, it is fabricated using discrete silicon-based transistors in order to transmit higher powers. Therefore it requires a large number of components (both active and passive).
Solution: Convert this circuit into an integrated GaN IC. In this way, not only the number of components used can be reduced but also high resonant frequencies can be achieved. Due to the increase in resonant frequency, it is also possible to reduce passive components and further improve the power density of the converter.
Results/Outputs: The integration of the circuit into a GaN IC chip was successfully implemented. The 2.5mm × 2.5mm area IC incorporates the switching cell of a Royer-circuit. The performance of the chip was tested using a wireless power transfer system. The operation of the system has been demonstrated at resonant frequencies up to 3MHz at input voltages reaching 60V and output powers of max. 100W. The combination of switching frequencies at 3MHz and an efficient converter design allows for a very compact and cost-effective WPT reaching efficiencies between DC_in and DC_out of up to 90%.
DOI: 10.1109/WiPDA58524.2023.10382227 – M. Rueß et al., “Multi-MHz Auto-Resonant Power Oscillator in a 650V GaN-on-SOI Technology for Compact Wireless Power Transfer Systems”, 2023 IEEE 10^th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Charlotte (NC), USA, 2023
Testimonial: “The realization of the integration of the presented self-oscillating resonant power amplifier was made possible by the ASCENT+ program. We gained access to imec’s 650V GaN-on-SOI MPW run and were able to successfully implement and fabricate our design. During the project, we received very good and very positive support, which greatly facilitated the implementation. “

ASCENT+ Access Project: ²⁸Si layer exchange for quantum computers (RefNo 228)
User: Ella Schneider
Affiliation: Ion Beam Centre, University of Surrey, Guilford, United Kingdom
Problem: Spin qubits hosted in cryogenically cooled, defect-free, isotopically pure ²⁸Si are extremely promising architectures for scaling up quantum computers. ²⁸Si atoms are spin-free, so a defect-free, cryogenically-cooled host ²⁸Si crystal acts a “semiconductor vacuum”, the ideal environment to preserve the delicate quantum states qubits. natSi is predominantly composed of ²⁸Si (92.2%) but contains 4.7% ²⁹Si and 3.1% ³⁰Si. The presence of ²⁹Si is particularly detrimental to the functionality of qubits due to its nuclear spin (½) which can disturb and interfere with qubits through spin-spin interactions.
Solution: An essential part of Si-based quantum computer fabrication is therefore ²⁸Si enrichment. In this work, we are developing an enrichment method that uses ion implantation and layer exchange. ²⁸Si is implanted into a Al Al on a native oxide free Si substrate.
Testimonial: “The ASCENT+ programme enabled access to Tyndall’s industrial fabrication facilities for research into my PhD work on implanted layer exchange enrichment for quantum computers. Collaborating with Tyndall’s experts and the high quality of the samples prepared at Tyndall helped to optimise and develop the enrichment process, significantly progressing the project.”

ASCENT+ Access Project: Characterisation of 2D-TMD devices (RefNo 227)
User: Ageeth Bol
Affiliation: Eindhoven University of Technology
Problem: Two-dimensional layered transition metal dichalcogenides (TMDs) like MoS2 are seen as promising materials for back-end-of-line applications in nanoelectronics including low-power devices. We can synthesize large-area polycrystalline MoS₂ at temperatures as low as 100°C, with or without the addition of a laser annealing step. To explore the full potential of the ALD synthesized MoS₂ at low temperatures, electrical devices have to be fabricated and characterised. The results will be used to further optimise the ALD processes.
Solution: The user fabricated MOSFET devices from MoS₂ grown in house. These devices went through a whole electrical characterisation, and extraction of MOS figures of merit; including: I_drain vs V_gate, subthreshold slope vs V_gate, I_drain vs V_drain, ΔI_drain vs ΔV_gate (i.e. g_m, transconductance), max g_m vs T, field-effect mobility and V_t extraction, field-effect mobility vs T, etc.
Results/Outputs: DOI: 10.1021/acs.chemmater.2c01154 – “Atomic Layer Deposition of Large-Area Polycrystalline Transition Metal Dichalcogenides from 100°C through Control of Plasma Chemistry” (Open Access)
DOI: 10.1016/j.sse.2023.108701 – Experimental analysis of variability in WS₂-based devices for hardware security” (Open Access)

ASCENT+ Access Project: Time-resolved diffuse x-ray scattering simulation (RefNo 213)
User: Sooheyong Lee
Affiliation: Korea Research Institute of Standards and Science, Daejeon, South Korea
Problem: Circumventing thermal diffusion to quickly direct heat transfer at nanoscale could enable new thermoelectric, optoeletronic, and photovoltaic devices. Despite decades of study, understanding and controlling microscopic heat flow remains elusive: nanoscale structures tend to trap heat, and thermal transport stagnates when heat sources are rapidly modulated. A major step toward addressing such complication necessitates obtaining more intrinsic picture of thermal energy and its distribution processes in materials.
Solution: Our time- and momentum-resolved measurement reveals a significant phonon population is generated at the zone edge in GaAs lasting up to hundreds of picoseconds. With the aid of state-of-art numerical simulation, we have learnt how our experimental observation can be explained by relevant intra-valley electron-phonon scattering and phonon-phonon decay processes.
Testimonial: “Our experimental and simulation result challenges the common notion that the zone-center optical vibrational mode is the sole dominant channel of energy from the electronic system to the lattice. We observe differing relaxation times of the non-equilibrium phonons between direct and in-direct semiconductors leading to the recovery of thermodynamic equilibrium, and that such atomic-scale interaction carries a notable impact on nanoscale heat transport at room temperature.”

ASCENT+ Access Project: MoS₂ transistors for cryogenic electronics (RefNo 208)
User: Michael Thompson
Affiliation: Lancaster University, United Kingdom
Problem: Many areas of scientific research require measurements of extremely weak electrical and magnetic signals. Given that most of such experiments are performed at low temperatures, there is a growing demand for low-noise instrumentation that can operate at cryogenic temperatures (4K and below).
Solution: Usage of MoS₂ FETs at temperatures down to 10mK for building cryogenic electronics.
Results: Samples of MoS₂ transistors were fabricated by the Access Provider and were then measured by the user. The main objective of the project was to understand the behaviour of MoS₂ field effect transistors (FETs) at ultra-low temperatures, and to learn about the performance of the MoS₂ material, and its limitations.
Testimonial: “Access through ASCENT+ was quick and easy and gave us access to materials and facilities that we do not have ourselves. Our project partners at the access site shared similar interests in understanding the behaviour of MoS₂ at cryogenic temperatures which made for a very collaborative project and not just samples as a service. Through this project we now have a better understanding of the performance and limitations of MoS₂ at ultra-low temperatures and potential avenues for further study.”

ASCENT+ Access Project: NV Centers in Diamond Nanostructure by Overgrowth (RefNo 207)
User: Mayeul Chipaux
Affiliation: École Polytechnique Fédérale de Lausanne, Switzerland
Problem: Improving the sensitivity of diamond Nitrogen-Vacancy (NV) centres techniques is essential to allow this promising technology spread into different branches of science such as in quantum sciences, nano-magnetism or biological sensing.
Solution: As a new fabrication method for diamond structures containing NV centers with high performances in terms of density and coherence time, we fabricated optimised nanopyramids by overgrowing NV center doped layers by chemical vapor deposition on nano-structured diamond samples.
Results: Successful growth of nanopyramids with thin layer of high quality NV centers. This is of very high interest toward diamond based quantum technologies
Testimonial: “We experienced a very efficient collaboration to produce original research requiring large facilities and associated expertise.”

ASCENT+ Access Project: Physical characterisation of innovative electrodes (RefNo 204)
User: Elixabete Ayerbe Olano
Affiliation: Cidetec, Donostia – San Sebastián, Spain
Problem: Advanced integration of innovative electrodes in solid state batteries requires good knowledge of their physicochemical properties. This is required to address degradation phenomena that could be understood to optimise their design. In this sense, it will be possible to increase the device performance and lifetime, deploying an economical and viable solution towards a safer, greener and more sustainable energy storage.
Solution: The characterisation carried out in this project helped us obtain relevant parameters for multiphysics degradation model validation to predict the behaviour of solid state cells.
Testimonial: “Our experience with ASCENT+ is very positive. We have access to new characterisation platforms to address the analyse of our innovative electrodes.”

ASCENT+ Access Project

TiN thin-film for silicon transistor (RefNo 202)

User

Miguel Fernando González Zalba

Affiliation

Quantum Motion, Harrogate, United Kingdom

Problem

Solid-state qubits require local electronics to detect the tiny readout signal coming from the active region of the device. The combination of both elements defines a qubit unit cell and its footprint determines the scalability of the technology.

Solution

We combine silicon spin qubits (embedded in field-effect transistors) with resonant superconducting electronics (based on high-kinetic inductance materials) to produce the world’s most compact qubit unit cell, all manufactured using industrial compatible processes.

Access provided: Access to Nanofabrication facilities at Tyndall.

Testimonial

“As part of this Access project, TiN thin film superconducting properties have been studied as a function of film thickness and growth method. The project aimed to determine the best combination of parameters for maximising the kinetic inductance of the films.”

Video Testimonial

Ascent Project Ref No: 157
User: Victor Kotlyar
Affiliation: Image Processing Systems Institute, the Russian Academy of Science, Russia
Description: It was planned to fabricate two meta lenses. One converts the polarization of the incident beam from a linear to a second-order polarization vortex and focuses the converted radiation. The second is intended for circular polarised incident light, the metalens converts it into a second-order phase vortex using spiral zone plate inside. A feature of these metalenses is that in the center of the focal spot an area with a reverse flow of intensity is formed. If a nano particle is placed into the such area, then it will experience scattering force from the light field in the opposite direction of the optical axis, that is, in the direction of the light source.
Thin film (115nm) of amorphous silicon (a-Si) was deposited on pyrex at the Tyndall National Institute. To create an e-beam mask and etching mask a ZEP resist was applied to the sample by a spinner. The Raith e-line e-beam system was used to create patterns in ZEP. ICP etching was performed to transfer the pattern into a-Si using SF6/C4F8 gases. Stripping of remained hard-etched ZEP mask was done using a 1165 solvent as well as oxygen asher.
The experimental work on the samples is in process.
The AFM images (with varying magnifications) show the surface of the metal. The diameter of the metal oxide is 30µm, the period of the structure is 220 nm, the relief depth is 115 m. This metalinza has a high numerical aperture and focuses laser light with a wavelength of 532nm into a subwavelength light ring.
Access provided: Remote access was provided to nano-fabrication facilities at Tyndall. In particular: Raith e-line e-beam lithography system, STS ICP etcher, oxygen asher, spinner, surface profiler Dektak.
Publication: V.V. Kotlyar, S.S. Stafeev, A.G. Nalimov, L. O’Faolain, and M.V. Kotlyar, “A dual-functionality metalens to shape a circularly polarised optical vortex or a second-order cylindrical vector beam”, Photonics and Nanostructures – Fundamentals and Applications, Vol 43, February 2021, 100898
DOI: 10.1016/j.photonics.2021.100898

STEM-EDX Image

Ascent Project Ref No

153

User

Kerim Yilmaz

Affiliation

NanoP, THM University of Applied Sciences, Giessen, Germany

Description

The Nanoelectronics Device Modeling Research Group, led by Prof. Dr. Alexander Klös, focuses on device simulation and compact modeling of different type of transistors.
My PhD research tasks include the development of physics related modeling approaches for nanowire transistor structures, in particular considering three-dimensional effects on the electrical behavior.
I received one quarter of a 300mm wafer from CEA-Leti to perform electrical characterisations with our wafer prober, especially on the narrowest SOI Ω-gate NW FETs with different channel length. Of interest are devices with short-channel characteristics such as DIBL, slope degradation or VT roll-off.
The developed compact model for short and long channel cylindrical gate-all-around (GAA) MOSFETs shows good agreement with TCAD Sentaurus simulation data. The experimental data will allow to calibrate the simulator and to evaluate and prove the accuracy and reliability of the developed compact model.
It is a physics based unified model which provides analytical solution for the potential in the channel and can be used for DG, FinFET and GAA MOSFETs with minor changes in the core model.

Access provided: One quarter of a 300mm wafer from CEA-Leti for electrical characterisation of SOI Ω-gate FETs.

Christoforos Theodorou at imec

Ascent Project Ref No

152

User

Christoforos Theodorou

Affiliation

IMEP-LAHC, Grenoble, France

Description

Christoforos Theodorou visited our imec labs in March. This collaboration arose from one of the very first collaboration of imec and IMEP-LAHC in ASCENT, with Professor Gerard Ghibaudo.
Firstly, access to the data collected on the automatic testers was granted. The low frequency noise behaviour for the 14nm bulk finFET technology devices provided by imec was characterised by measuring various figures of merit on the imec test setup for a week. This work, which started with a hands-on session the first day, will now continue at the user’s facility, using the silicon provided by imec. For this purpose, 3 wafers will be exchanged, and a series of analytical low frequency noise and random telegraph noise measurements will be performed.
The results of this work supported by ASCENT will allow to benchmark the test setups providing a set of guidelines for noise measurements, as well as to develop accurate finFET compact noise models suitable for circuit simulations.

Access provided: Electrical characterisation of 14nm finFET technology at imec.

STEM-EDX Image

Ascent Project Ref No

150

User

Dr. Lynette Keeney

Affiliation

Tyndall National Institute, University College Cork, Ireland

Description

Multiferroic materials, possessing simultaneous electric and magnetic memory states, have been road-mapped as promising multi-state architectures for data-storage scaling beyond current technologies.
In order to optimise one such material system (Aurivillius phase Bi₆Ti_xFe_yMn_zO₁₈) for future miniaturised data-storage technologies, I recently synthesised multiferroic thin film samples at sub-10 nm dimensions.
However, analysis of thin film composition becomes more difficult at reduced dimensions.
Thanks to the ASCENT Network and the microscopy skills of Dr. Zineb Saghi from CEA-Leti, chemical composition analysis of the ultra-thin Aurivillius phase layers was enabled using high resolution STEM (scanning transmission electron microscopy) and EDX (energy dispersive X-ray analysis). This work demonstrates that Mn and Fe, essential to the multiferroic properties, have successfully been incorporated into the ultra-thin layers.

Access provided: High resolution TEM and STEM with EDX at CEA-Leti.

TEM Image High Resolution TEM Susana Devesa

Ascent Project Ref No

146

User

Susana Devesa

Affiliation

Physics Department of University of Aveiro and I3N, Aveiro, Portugal

Description

I am working with bismuth and lanthanide-based materials, being my main objective the dielectric characterisation of these ceramic materials. However, for a better understanding of the dielectric properties of a material, it is important to know their structural properties. One of these properties is the crystallite size, that can be determined using different models.
The confirmation of the results obtained with the applied models is very important, mainly because in one of the models, the Uniform Deformation Energy Density Model (UDEDM), we used parameters that are approximations since they have not yet been reported for the Bi_1.34Fe_0.66Nb_1.34O_6.35 phase.
Thanks to the ASCENT Network, it was possible to obtain TEM and HR-TEM images that allowed the estimation of the distance between adjacent planes in the Miller indexes and the estimation of the crystallite size. In addition to this process, EDX was also performed.

Access provided: High Resolution Transmission Electron Microscope (HR-TEM) at CEA-Leti.

imec Cu pillars imec mask design Wafer list imec process

Ascent Project Ref No

145

User

Daniel Smallwood

Affiliation

Tyndall National Institute, Cork, Ireland

Description

The main goal of the project was to develop an optimised process for utilising Cu pillars in lieu of through substrate vias (TSVs), or to enable the additive deposition of TSV technology. This method removes the need for deep reactive ion etching (DRIE) of the substrate, where the side walls of DRIE etched TSVs are scalloped and the via cross sections have gradated diameters along their axial length. Electrochemically depositing Cu into TSVs is difficult, as current crowding at the via entrance causes heterogeneous deposition rates, often resulting in a dual pyramidal shape of the deposited material. Conversely, electrochemically depositing Cu into feature holes created by lithographic processing is free from all of the aforementioned problems. Lithographic processing is ideal, as the process can be tuned to create a vertical and non-gradated resist profile along the axial length of the feature holes and additionally, current crowding is a non-issue because the deposition is uniaxial in the z-direction.
The first results comprise SEM micrographs of the diced wafers, which have been investigated for pillar side wall and height profiles, as well surface roughness. The pillar side walls were found to be retrograde, with significant variability in the cross-sectional diameter from substrate contact to pillar apex (ex. 70-97µm). In the case of the Cu pillars being used as interconnects, the electrical resistance (R ∝ A-1) will be increased according to the magnitude of the cross-sectional variance.
The pillar height is variable across the wafer, which is due to a changing current density across the die, as corresponds to a variable local feature density. Images were taken with θ = 68°, which corresponds to an actual pillar height of 124µm. The apex of the pillars is over-plated, indicating the photoresist was spun to ≈124µm. Future plans involve utilizing CMP to remove the over-plated material and/or the retrograde side-walls to improve pillar performance by eliminating undesired short circuits and reducing pillar size for increased integrability, whilst maintaining a constant resistance along the axial length.
Pillar circumferential roughness is low (single-digit µm to nanoscale regime), contrary to the conventionally very rough scalloped profile formed as a result of utilising DRIE for via fabrication.

Access provided: 12×12″ wafers with Cu pillars plated at variable diameters and densities. The wafers were stopped at various stages along the process fab for a greater depth of pillar characterisation at imec.

Ascent Project Ref No

143

User

Mandar S. Bhoir

Affiliation

Department of Electrical Engineering, Indian Institute of Technology Gandhinagar (IIT GN), India

Description

The project had several objectives:

To investigate the impact of thin BOX and Ground Plane doping on transistor’s non-linearity and on low frequency noise
To model the investigated behaviors of noise and non-linearity on top of existing compact FDSOI model to make them more robust and accurate

For that several kind of measurements were performed and analysed. I/V full set were measured and further using derivative techniques, second and third harmonics performances were calculated and compared to high frequency measurements at ~1 GHz for various back gate voltage conditions.
Low frequency noise measurements were also performed. The contributions of noise due to trapping at front interface and at back interface as well as the correlated mobility noise were discussed.

Access provided: ASCENT provided data of I(V), C(V), high frequency linearity and low frequency noise performed by CEA-Leti on 20nm FDSOI transistors.

Susana at Tyndall Dielectric Constant vs Frequency

Ascent Project Ref No

137

User

Susana Devesa

Affiliation

Physics Department of University of Aveiro and I3N, Aveiro, Portugal

Description

I am working with bismuth and lanthanide-based ceramics, being my main objective the dielectric characterisation of these materials.
Thanks to the ASCENT Network, it was possible to measure the dielectric constant and the dielectric losses in a large microwave frequency range, at two and three different temperatures.
The measurements were performed in eighteen samples, using a dielectric probe, with ε’ and ε” extracted using the Keysight Technologies’ software.
These measurements complemented the dielectric characterisation of the samples, enabling the determination of the temperature coefficient of resonant frequency, which is a key parameter for dielectric characterisation.

Access provided: Remote access to dielectric characterisation at Tyndall.

FIB/TEM Lab

Ascent Project Ref No

136

User

Christian Pinto Gómez

Affiliation

Barcelona Microelectronics Institute (IMB-CNM), CSIC, Spain

Description

Structural characterisation of directed self-assembly of block co-polymners Silicon nanowires (SiNWs)

Access provided: Lamella sample preparation by focussed ion beam (FIB) followed by high-resolution transmission electron microscopy (HR-TEM) at Tyndall.

Watch Christian’s story:

Ascent134_1 Ascent134_2 Ascent134_3

Ascent Project Ref No

134

User

Jordi Muñoz Gorriz

Affiliation

Departament d’Enginyeria Electrònica
Universitat Autònoma de Barcelona, Spain

Description

Reliability analysis of thin oxide films for microelectronic devices relies almost exclusively on electrical measurements. The application of ramped or constant voltage stress to MIM and MIS structures generates defects which results in the formation of a short across the insulating layer. If the energy released during this event is high enough, the damage becomes visible as a mark on the top metal electrode of the structure. The set of marks generated in a single device can be mathematically treated as a point pattern. In this work, standard electrical characterisation (I-V, TDDB, etc.) was complemented with a statistical analysis of the breakdown spot distribution. We have made use of spatial statistics methods such as intensity plots, pair correlation analysis, distance histograms, etc. Thanks to the ASCENT project we were able to record videos in the infrared spectrum showing the microexplosions associated with the appearance of the spots. This allowed us to investigate not only the location of the failure sites but also their size and generation time. The thermal images provided us valuable information for the development of a finite-element thermal model of the filamentary current path. The devices were fabricated at Tyndall National Institute, Ireland and were characterised at CEA-Leti, France.

Access provided: Infra-red characterisation at CEA-Leti.

FIB/TEM LabPhoto

Ascent Project Ref No

133

User

Paloma Tejedor

Affiliation

Instituto de Ciencia de Materiales de Madrid (ICMM-CSIC), Madrid, Spain

Description

Research activities at the Laboratory of III-V Semiconductor Materials focus on nanoscale selective area growth by molecular beam epitaxy (MBE) of III-V compounds with high mobility and strong spin-orbit coupling (InAs, InGaAs, InSb, …) for their application in electronic and quantum technologies. Presently, our group is engaged in the development of Si CMOS-compatible processes to grow vertical nanowires for tunnel field effect transistors (VTFETs) and scalable arrays of interconnected qubits based on in-plane grown nanowires for topological quantum computing.
Thanks to the ASCENT Network we have had access to the fabrication by electron beam lithography and selective etching of HfO₂ and SiO₂-masked Si (111) nanostructured substrates having feature sizes as low as 40nm, where we are studying the effect of mask composition on group III adatom diffusion, the formation of antiphase domains and threading dislocations as well as atomic interdiffusion during the selective nucleation and growth of InGaAs/Si and GaSb/InAs/Si nanowire-based heterojunctions by MBE. Due to the variety of feature sizes and pith dimensions present in the nanotemplates, the number of MBE experiments needed to optimize the nanowire morphology and structure is greatly reduced.

Access provided: Nano-fabrication of two 2″ nanostructured HfO₂/Si(111) and SiO₂/Si(111) wafers at Tyndall.

Compact Trap Model — *Small-signal equivalent circuit*

CV Graph — *Trap-to-Gate Conductance effect on CV characteristics*

Ascent Project Ref No

130

User

Andrzej Mazurak

Affiliation

Warsaw University of Technology, Institute of Microelectronics and Optoelectronics, Poland

Description

The most common approach to characterise interface or border traps in MIS structures is to measure the gate capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics of a fabricated MIS capacitor or transistor over a wide range of frequencies. An extraction method of traps parameters can be based on different models of the MIS structures, taking into account various charge and discharge mechanisms of traps. The models proposed in literature are usually based on a Nicollian-Brews’ equivalent circuit of a MIS capacitor modified by addition of tunnel exchange paths between the traps and the semiconductor bands and eventually tunnel paths between the gate and the substrate conduction and valence bands. However, they do not comprise charge communication between the traps and the gate electrode. Our group developed a model enhanced by including tunnel communication between the gate and the traps. The model enables to assume an arbitrary discrete distribution of trap states over energy and position in the gate stack and thus it is valid for surface, border and bulk traps. The measurement data obtained via ASCENT was used for model validation.
The results have been accepted for an oral presentation at the Insulating Films on Semiconductors 2019 Conference, Cambridge, UK. Two papers were published (DOI:10.1116/1.5060674, DOI:10.1016/j.mee.2019.111011). The work on model development will be continued.

Access provided: Measurement data of admittance (C-G-V-(T)) and current-voltage (I-V-(T)) characteristics for sample structures fabricated and measured by CEA-Leti (p-Si MOSFET transistors with TiN/HfO₂/SiO₂ gate stack).

Raman map measurements on VO2 — *Raman map measurements on VO₂ patch following the red line*

*RF measurements (S21 parameter) on Shunt device, T=30°C → 80°C → 50°C*

Ascent Project Ref No

121

User

Guy Garry / Olga Ishchenko

Affiliation

TE-OX, France

Description

TE-OX aims at manufacturing novel optically controlled microwave switches and related devices (phase shifters and reflect arrays) by integrating VO₂ thin films in coplanar lines taking benefit of the Metal-Insulator phase transition (MIT).

TE-OX have designed new architectures in order to decrease the switching-time down to the ns and sub-ns scales by triggering the transition respectively by an electrical field or optical absorption. In both cases one needs to optimize the VO₂ thickness and, as a consequence, optimize the geometrical parameters of the coplanar lines.
Therefore, the main goal of the project was to investigate the switching time of thermally induced VO₂-based RF switches. The RF-devices fabricated on VO₂ thin films of different thicknesses were measured on VNA up to 40GHz at different temperatures (RT to 80°C and back to 50°C). To further gain insights of the VO₂ transition in these devices, Raman characterisations and SEM observations were performed.

Access provided: Electrical, physical and optical characterisation (microwave S-parameters measurements up to 40GHz and 80°C, SEM and Raman Spectroscopy) at Tyndall.

Theodoros A. Oproglidis Test wafer IdVg Characteristics

Ascent Project Ref No

119

User

Theodoros A. Oproglidis

Affiliation

Aristotle University of Thessaloniki, Department of Physics, Thessaloniki, Greece

Description

The goal of this project is to investigate the variability of triple-gate junctionless transistors fabricated in imec, Belgium. ASCENT network provided the opportunity for a week’s visit to measure I-V characteristics from a large number of transistors in order to assess both local (matching pairs) and global variability. For this reason, various device technologies were selected. For the local variability investigation, channel length varies from 28nm to 34nm and for global variability from 26nm to 90nm for different number of fins. The devices’ fin width, fin height and channel doping are fixed and equal to 9nm, 40nm and 1.5×10¹⁸ cm^-3 respectively.

The first results have confirmed the expected variability challenge for the triple-gate junctionless transistors, mainly due to their ultra-high doped channel. Our previous analytical compact model was formulated in order to be continuous and symmetric (verified using the Gummel Symmetry Test – GST) and is used to extract the ideality factor, threshold voltage, mobility, series resistance and the channel length modulation parameter from the variability measurements. The results following the statistical analysis of the aforementioned variables will be used to assess the sources of variability as well as predict the variability in the device performance.

Access provided: I_d-V_g measurements to investigate the variability of nanoscale triple-gate junctionless transistors at imec.

Mandar S. Bhoir imec characterisation lab

Ascent Project Ref No

113

User

Mandar S. Bhoir

Affiliation

Department of Electrical Engineering, Indian Institute of Technology Gandhinagar (IIT GN), Gandhinagar, 382355, India

Description

My PhD research is focused on investigating the challenges and optimization of advanced CMOS devices from Analog/RF perspective. Process induced variability has been one of the challenges in scaled CMOS technologies resulting in performance mismatch and hampering production yield. The goal of this project was to experimentally investigate different variability sources and evaluate their impact in advanced FinFET technologies.

Through ASCENT, I got access to imec’s sub-10nm fin-widths FinFET technology and characterisation infrastructure. During my imec visit, I received training on different characterisation setups (semi-automatic and manual), essential to carry out extensive measurements for variability analysis. Automatic probers have also been used for measurement. Also, the extensive technical discussions with the researchers at imec were quite helpful. The results so far are interesting and highlight key process induced variability sources. We came up with a research paper based on this work (DOI:10.1109/EDTM.2019.8731200) and are planning follow-up interactions.

Overall, the ASCENT project from proposal to on-site access went on quite smoothly and has positively contributed towards my PhD thesis.

Access provided: Access to imec’s FinFET technology and visit to characterisation infrastructure.

TEM Cross Section Olivia Hendricks

Ascent Project Ref No

105

User

Olivia Hendricks

Affiliation

Department of Chemistry and Department of Materials Science and Engineering, Stanford University, Stanford (CA), U.S.A.

Description

Metal-insulator-semiconductor (MIS) junctions are a promising photoelectrochemical cell design that electronically couple a high-quality semiconductor to an efficient water oxidation catalyst. The photovoltage produced by an MIS junction depends on the strength of the built-in field, or Schottky barrier height. For an n-type silicon photoanode, a high work function metal induces a field that sweeps photogenerated holes to the electrolyte interface for water oxidation.
TiO₂-IrO_x alloys grown by atomic layer deposition are promising Schottky contacts for n-type silicon photoanodes. These alloys possess a high work function, generating photovoltages of over 600 mV. The ASCENT Network allowed us to assess the morphology and uniformity of ALD TiO₂-IrO_x alloys on silicon using transmission electron microscopy (TEM). While we were able to probe the photoanode structure by many methods, such as X-ray reflectivity and electrochemical impedance spectroscopy, the cross-sectional TEM performed at Tyndall allowed us to directly characterise the structure of the film. These results were included in our latest paper:
O. Hendricks, R. Tang-Kong, A. S. Babadi, P. C. McIntyre, C. E. D. Chidsey, “Atomic Layer Deposited TiO₂-IrOx Alloys Enable Corrosion Resistant Water Oxidation on Silicon at High Photovoltage”, Chemistry of Materials, 2019, 3 (1), pp. 90-100 (DOI:10.1021/acs.chemmater.8b03092)

Access provided: Remote access to cross-sectional transmission electron microscopy (TEM) at Tyndall.

Simone Iadanza poly-Si Photonic Crystal

Ascent Project Ref No

104

User

Simone Iadanza

Affiliation

Centre for Advanced Photonics & Process Analysis, Cork Institute of Technology, Cork, Ireland

Description

The aim of my PhD is to develop a new family of low power optical interconnects such as modulators lasers and photo-detectors using photonic crystals patterned on deposited silicon, vertically integrated to the electronic chip without consuming area of the latter.
A 1µm thick layer of silicon dioxide (SiO₂) has to be thermally grown on a carrier silicon wafer first. A 220nm thick layer of amorphous silicon using low-pressure chemical vapour deposition (LPCVD) has to be deposited at 580°C. The wafer has to be then annealed in forming gas, which transforms the amorphous silicon into polycrystalline silicon, and then patterned. One of the primary challenges is to develop high quality optical resonators in deposited silicon due to the relatively high surface roughness of polycrystalline silicon (~10nm). CEA-Leti LPCVD and Chemical-Mechanical Polishing capabilities allowed the fabrication of smooth and uniform poly:Si for the development of the high Q optical resonator, with a surface roughness in the sub-nanometre range.

Access provided: LPCVD of a:Si, annealing into poly:Si and CMP processing at CEA-Leti.

Alexei Nazarov SiNWs Test Structure

Ascent Project Ref No

103

User

Alexei Nazarov

Affiliation

Lashkaryov Institute of Semiconductor Physics NASU, Kyiv, Ukraine

Description

The department of Functional materials and nanostructures in Lashkaryov Institute of Semiconductor Physics NAS of Ukraine is one of leading department operating in development of plasma-related technologies for annealing of defects and material ordering at low temperatures (up to 200C). Especially this technology is useful for thin-film and nanostructured devices. In frame of the Ascent project we had opportunity to fabricate Si nanowires (NWs) on SiO₂-Si wafer in Tyndall and to perform their electrical characterisation during one week visit of Tyndall. Plasma treatment was performed in Ukraine. Obtained results have shown possibility of the plasma treatment to diffuse doping impurity from surface to bulk of the silicon NWs at low temperature and decrease of contact resistivity between metal contact and Si NW. Equipment which located in Tyndall characterisation Lab allowed us to perform fast and comprehensive electrical characterisation of the devices.

Access provided:Electrical characterisation Lab and Silicon Nanowires (SiNWs) test devices at Tyndall.

Aleksandar Pajkanovic RF Probes Network Analyser

Ascent Project Ref No

100

User

Aleksandar Pajkanovic

Affiliation

Faculty of Electrical Engineering, University of Banja Luka, Bosnia and Herzegovina
Faculty of Technical Sciences, University of Novi Sad, Serbia

Description

Meander-type inductors are designed and fabricated in silicon and flexible technology to investigate the performance of this topology and the possibilities of its utilization in RF applications. The CMOS inductor is fabricated using a standard 130 nm technology node and characterised on-chip using a measurement set-up including: wafer probe station, various probes and VNA. Among the most important characteristics of ICs are its PVT variations, which stands for process, voltage and temperature. As this inductor is a passive component, the voltage variations are not discussed. The process variations have been characterised, reported and commented within the paper:

Microelectronics Journal (DOI:10.1016/j.mejo.2016.07.016)

Via ASCENT project, we were granted the possibility to characterise temperature variations of the designed component. In this way, we would complete PVT variation analysis of the designed inductor, thus gaining valuable knowledge required to improve the design phase of such inductors in future. Results have been published within the paper:

15^th SMACD Confererence, 2018 (DOI:10.1109/SMACD.2018.8434918)

Access provided: Remote access to RF probe station with a temperature controllable chuck and VNA at Tyndall.

Ascent Project Ref No

089

User

Luis Guillermo Villanueva / Martin Hegner

Affiliation

Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland

Description

Silicon cantilever arrays for label-free diagnostics. The aim of this project is to generate a new type of silicon cantilever arrays with up to 18 sensors per chip for nanomechanical diagnostic investigations. Increasing from a previous design of 8 to 18 sensors on one chip allows to implement multiple target and reference probes in parallel enabling differential readout and improved statistical analysis. A movable laser source will be utilised to readout the nanometer motion of the end of the single clamped beams. The sensor beams will be oscillated at a higher mode in fluids in the MHz regime. These sensors will be used to measure specific interactions of biological analytes in physiological environments.

Access provided: Nano-fabrication of Si cantilever devices at Tyndall.

Jae Woo Lee Noise characteristics

Ascent Project Ref No

087

User

Jae Woo Lee

Affiliation

Dept. of Electronics & Information Engineering, Korea University Sejong Campus, Sejong, South Korea
ICT Convergence Technology for Health & Safety and Department of Electronics and Information Engineering

Description

Thanks to the support from ASCENT program, I have been collaborated with IMEP-LAHC and CEA-LETI in ASCENT with Professor Gerard Ghibaudo and Dr. Sylvain Barraud for the low frequency noise variability analysis of omega-FET.
Recently, due to the aggressive device scaling down, developing next technology node is faced to extremely difficult conditions such as short channel effects and process variations. One of them, because controlling VT uniformly is hard in down scaled devices, the variability of VT (AVT) has been studied to figure out reliable device performance. Likewise, for the reliable device performance of logic application, the reduction of low frequency noise is necessary. Thus, the study of noise variability is important to develop advanced device technologies. In this study, I’m working on that the LFN variability of GAA FETs with different channel (Si vs. SiGe) to quantify the variability of noise and to understand its origin with statistical analysis.
This study has been reported in The 26^th Korean Conference on Semiconductors (TB1-G-7) and been prepared for the SCI journal paper.

Access provided: 300mm Wafer with nanowires of geometries down to ∼10nm supplied by CEA-Leti.

Ascent Project Ref No

081

User

Martino Aldrigo / Mircea Dragoman

Affiliation

National Institute for Research and Development in Microtechnologies (IMT), Bucharest, Romania

Description

The Laboratory for micromachined structures, devices and microwave circuits at IMT Bucharest is leading research in the domain of microwave and millimetre-wave devices with potential applications in aerospace, automotive, ambient sensing and energy-harvesting for next generation internet-of-things (IoT). In view of the high data-rate capabilities offered by 5G technologies, a major challenge is the fabrication of efficient antenna-rectifying diode (“rectenna”) systems, able to work in presence of low input power levels (less than -10 dBm) at high frequencies (i.e. 60 GHz and above). The optimal solution that we found was the integration of a hafnium-based metal-insulator-metal (MIM) diode with a gold/platinum bow-tie antenna on standard high-resistivity silicon/silicon dioxide substrate. This device is perfectly CMOS compatible and shows an excellent responsivity of over 5 V/W with a harvested voltage of almost 250 microvolt.

Thanks to ASCENT Network, we could fabricate at Tyndall on a 4-inch Si wafer (with deep-UV optical lithography) the rectennas comprising a 6-nm-thick hafnium-based MIM diode. The devices were then characterised by using a High Resolution Transmission Electron Microscopy (HRTEM) facility to investigate potential imperfections in the multi-layer stratification (depth profiling). Finally, a complete DC and RF characterisation was performed to test the harvesting capabilities at millimetre waves.

Access provided: Fabrication of MIM devices at Tyndall. Followed by characterisation (both physical -High Resolution Transmission Electron Microscope- and electrical at radio frequencies).

Ascent Project Ref No

079

User

Michael Schroeter & Paulius Sakalas

Affiliation

Technische Universität Dresden, Germany

Description

The goal of this project was the experimental characterisation of RF MOSFETs consisting of measuring the high-frequency behaviour over the circuit application relevant bias range.
Standard DC (transfer and output) characteristics were measured first. Then, S-parameters were measured over a frequency range of 1 to 67 GHz. Compared to similar 28nm CMOS technologies, the S-parameters of the measured samples/mask-set showed insufficient gain (S21) and a relatively high input impedance. Therefore, no further investigations were performed.
A second wafer exchange would have been required on a second set of samples to reach better figures of merit, but this was not pursued.
ASCENT provided an estimation of realistic RF characteristics of advanced MOSFETs and a possible comparison to emerging FET technologies.

Access provided: Access to imec’s RF MOSFET technology and characterisation infrastructure.

Ascent Project Ref No

077

User

Marco Grande

Affiliation

Politecnico di Bari (Technical University of Bari), Italy

Description

The nPEG group at Politecnico di Bari deals with the design and characterisation of integrated plasmonic, photonic and microwave devices combined with two-dimensional materials (e.g. graphene) for sensing and telecommunication applications.
We proposed and optimised silicon nitrate based nanobeam cavities obtaining high Q-factor of the order of 100,000 operating at both 1 µm and 1.5 µm. In particular, by engineering the nanobeam, we demonstrated how to fully control the Q-factor in “asymmetric” environments where the cavity is embedded in a low refractive index medium (e.g. liquid or gas).
These results defined a novel experimental platform for the realization of innovative optical cavities for sensing and optical interconnection since silicon nitride is particularly attractive due to its transparency in the visible range (and over 800-1000nm wavelength range) and biocompatibility.
Thanks to ASCENT Network, we could fabricate at Tyndall a full set of silicon nitride based optical nanobeam cavities with subwavelength nanostructures by means of a combination of electron beam lithography and dry etching. The silicon nitride layers were also deposited at Tyndall by means of PECVD. The experimental measurements carried out at CIT confirmed the numerical findings.

Access provided: Fabrication of optical devices at Tyndall by means: thermal oxide + PECVD SiN deposition, laser wafer dicing, EBL patterning, dry etching and SEM characterisation.

Ascent Project Ref No

076

User

Montserrat Nafría Maqueda

Affiliation

Universitat Autònoma de Barcelona, Barcelona, Spain

Description

In this project, the Reliability of Electron Devices and Circuits research group at the Electronic Engineering Department of the Universitat Autònoma Barcelona carried out the characterisation and modelling of time-dependent variability (TDV) in advanced FDSOI technologies. In particular, Random Telegraph Noise (RTN) was investigated, as a function of the gate and body bias voltages. Its relationship with ageing mechanisms such as Bias Temperature Instabilities (BTI) and Channel Hot Carrier (CHC) degradation were addressed.
To carry out this research, a 300mm wafer with SOI Nanowires with dimensions down to ∼10nm was provided by LETI.
First part of the study was performed and supported by ASCENT and will continue in the framework of a Spanish research project, where compact models suitable for circuit simulations will be developed.

Access provided: 300mm wafer with nanowires provided by CEA-Leti.

Ascent Project Ref No

074

User

Panagiotis Dimitrakis

Affiliation

Institute of Nanoscience & Nanotechnology, Demokritos, Aghia Paraskevi, Greece

Description

ASCENT Network provided the opportunity for a one week visit in LETI Electrical Characterisation Laboratory to perform extensive measurements on LETI nanowires.

Dr Dimitrakis had one-day training in the use of Cascade 300mm wafer prober and measurement software. Following, he had the chance to realize full I-V characterisation of large number of Silicon nanowire transistors to analyse the mobility statistical variation as well as to perform specific I-V measurements at different temperatures. Due to the completeness and the state-of-the-art equipment offered by the host laboratory at CEA-leti he was able to carry out many different experiments, to apply many different characterisation techniques and collect a significant amount of data during his short stay visit. His interaction with the experts in the lab was of special importance in order to develop links for further research collaborations in the near future.

A 300mm wafer with sub 10nm nanowires on Silicon-on-insulator technology was provided for complementary measurements, modeling and research at Demokritos. These devices should also be used for students training.

Access provided: Electrical characterisation Lab of CEA-Leti interactions with experts + Nanowires devices.

Ascent Project Ref No

072

User

Giuseppe Alessio Verni

Affiliation

Material Chemistry and Analysis Group, University College Cork, Cork, Ireland

Description

The Materials Chemistry and Analysis Group (MCAG) of UCC, led by Prof. Justin Holmes, is an active and diverse research group which focuses on the development of methods for the synthesis of nanostructured materials and their in-depth characterisation by advanced electron microscopy and surface analysis techniques. Research in the group ranges from nanowire fabrication using top-down/bottom-up routes, to colloidal nanoparticle synthesis.

Through ASCENT network, we made use of the TOF-SIMS facility in CEA-leti to characterise GaN wafers doped using molecular layer doping (MLD). MLD is an alternative doping technique where dopant-containing molecules are bound to the surface of a semiconductor; the semiconductor is then annealed, and the dopant is in-diffused from the surface leading to conformal and damage-free doping.

Access provided: Dopant characterisation at CEA-Leti using TOF-SIMS.

Ascent Project Ref No

070

User

Maart van Druenen

Affiliation

Material Chemistry and Analysis Group, University College Cork, Cork, Ireland

Description

Monolayer doping (MLD) is an alternative doping approach that attaches dopant precursors using surface functionalization, followed by a rapid thermal anneal which drives the dopant into the substrate. Oxide functionalization provides an easier method of attaching inexpensive, non-toxic dopant precursors compared to hydrosilylation, making this approach attractive for industrial applications. The overall aim of the project was to quantify the carbon content in Si wafers doped using a phosphorus oxide-MLD process. SIMS analysis gave an indication of phosphorus doping levels and confirmed carbon levels were higher in the oxide cap compared to the underlying Si substrate, demonstrating the oxide-MLD process results in minimal carbon contamination.
Results were published in: “Functionalization of SiO₂ Surfaces for Si Monolayer Doping with Minimal Carbon Contamination.” (DOI:10.1021/acsami.7b16950)

Access provided: SIMS measurements and analysis performed at CEA-Leti.

APT & Leti — Atom-probe tomography in Leti

Needle shaped specimen made with HfSe₂ and initial results from the Atom-probe tomography

Ascent Project Ref No

069

User

Gioele Mirabelli

Affiliation

Tyndall National Institute, University College Cork, Cork, Ireland

Description

The objective of the work was to investigate the reactions that take place on the surface of 2D-semiconductors after air exposure. These semiconductors are found in the form MX₂, where M is a transition metal (Mo, Hf, W, etc.) and X is a chalcogen (S, Se or Te). The metal reacts with oxygen, and this oxidised species is present on the surface of the sample. The chalcogen does not seem to react with oxygen, but is pushed away from the surface forming “protrusions” on the surface (DOI:10.1063/1.4963290). Information on how the material changes over time can clarify the reason of such behavior and open a way of possible solutions to prevent this. Atomic Probe Tomography can give an insight at a scale that is not possible to obtain otherwise. In particular two characteristics of these protrusions are of interest:

The material composition of the protrusions;
The interface between the protrusion and the oxidised metal;

The results pointed to a highly sensitivity and fragility of these protrusions, which are still subject of further studies.

Access provided: Atomic Probe Tomography (APT) at CEA-Leti.

Ascent Project Ref No

067

User

Carlos Márquez/Prof. Francisco Gámiz

Affiliation

Universidad de Granada, Spain

Description

Thanks to Ascent 067 Project, we have carried out the metallization and processing of MoS₂ (a transition metal dichalcogenide) back-gate transistors. Due to the layered van der Waal structure and its thin thickness, this material inside the two-dimensional materials family, presents outstanding properties in terms of electrical mobility, electrostatic control of the channel and indirect to direct bandgap depending on the thickness. Properties which make it suitable for a wide range of electronic, optoelectronics and bio-sensing applications. This thin layered material was synthesised following a scalable chemical vapour deposition process at the Nanoelectronic Laboratory, University of Granada, Spain and then metallised and processed following standard CMOS optical lithography at Tyndall National Institute, Cork, Ireland. Despite the theoretical promising properties, experimental devices do not usually fit with the expected performance. As in other technologies (Si, III-V, nanowires …) grain boundaries, dangling bonds, interface traps and defects play an important role in the actual electrical properties of the electronic devices. However, these phenomena are not entirely understood. Therefore, the aim of this project was to shed light into the instability effects which disrupt the performance of MoS₂ transistors through the electrical and structural characterisation of devices fabricated and processed following scalable methods.

Access provided: Optical lithography, SEM microscopy and on-wafer electrical characterisation equipment have been provided at Tyndall.

Ascent Project Ref No

064

User

Takashi Teranishi

Affiliation

Okayama University, Okayama, Japan

Description

Dielectric properties in ferroelectrics are dominantly determined by the dipole polarization; the polarization due to dipole switching in the ferroelectric domains/polar nano regions (PNRs). The dipole relaxation appears in a few to tens of GHz range, whereas relatively large metal electrode loss suppresses the upper frequency limit for the dielectric measurement in general.
The objective of this project is to determine microwave dielectric constant up to tens of GHz utilizing coplanar transmission line for ferroelectric ceramics. The method has been found to work quite nicely in the extraction of permittivity for dielectric substrates. For high dielectric constant substrates the longer and thinner signal lines produce more accurate results.
Microwave dielectric properties of Sn-loaded (Sr, Ba)Nb2O6 (SSBN) were evaluated. For the SSBN samples, we have not seen a clear increase in permittivity with Sn loading but there is an increase in surface pitting with increase in % Sn. Perhaps the increasing porosity leads to increased charge storage but the Transmission line extraction needs very uniform samples.

Access provided: RF Probe station (50-100 GHz range) and Network Analyser at Tyndall.

Ascent Project Ref No

059

User

Prof. Alexei Nazarov

Affiliation

Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences, Ukraine

Description

This project applied low-temperature plasma annealing (not more 250°C) to new types of semiconductor MOS devices such as junctionless III-V MISFET which are very sensitive to high-temperature processing.
Testing of interface and border traps in the interface Al₂O₃/InGaAs, channel electron mobility, source-drain contact resistance and channel resistivity and leakage current through InGaAs/InP heterojunction will be performed before and after low-temperature plasma annealing to extract an optimal regime of the annealing and demonstration of possibilities of the technology.The project will allow to develop a new approach to control of main electrical parameters of such nanoscaled devices.

Access provided: Nanoscale test devices and advanced electrical characterisation facilities at Tyndall.

Watch Alexei’s story:

Ascent Project Ref No

055

User

Nobuyuki Takeyasu

Affiliation

Okayama University, Okayama, Japan

Description

It is significant to control the shape of metallic nanostructures in plasmonics. Top-down approaches, such as electron-beam or focused ion beam lithography etc., enable metallic nanopatterning in nanoscale resolution. On the other hand, it is able to self-assemble Ag/Au nanoparticles (NPs) into a two-dimensional (2D) array over >cm², which is referred to as bottom-up approach. The 2D AgNP array is applicable to surface-enhanced Raman spectroscopy (SERS) as SERS active substrates. In this project, we fabricated 2D double-layered AgNP array with one-by-one deposition. The surface and cross-section of the fabricated AgNP arrays were observed with a SEM/TEM also with FIB for cross-section observation. The SEM observation revealed that the fabricated AgNP array was partially broken although this could be caused by the property of silicon substrate different from glass. Based on the results, we switched to one-step deposition for double-layered AgNP array. Recently, we evaluated the extinction properties of the single-, double-, and triple-layered AgNP arrays, and measured SERS with them.

Access provided: FIB+TEM/SEM (Physical characterisation) and Raman spectroscopy (Optical characterisation) at Tyndall.

Ascent Project Ref No

054

User

Laurent Artola

Affiliation

ONERA, France

Description

This goal of the project was to characterise the sensitivity of the 14nm FinFET technology against radiations with the aim to anticipate their use in embedded applications such as drones or nanosatellites. The effects of radiations on basic devices such n-MOS, p-MOS transistors are analysed. Various electrical parameters of these devices (leakage current, threshold voltage …) are measured and analysed to quantify their degradation due to radiations. The irradiation tests are performed at ONERA. The Cobalt60 facility allows for generating ionizing dose effects in devices. I/V measurements were performed on 2 lots of samples before and after irradiations. The first results have shown a strong degradation of the leakage current after an irradiation of about 500krad. This radiation level corresponds to 30 times of the equivalent dose received by the embedded systems in Earth orbit. The degradation trend of the degradation is relevant with the current works in progress on other FinFET technologies/processes. However, several samples of the tested lots were damaged (especially the bonding due to packaging step and/or transport). This has limited the statistic of irradiated samples. Additions samples were fabricated and packaged at IMEC and should be tested at ONERA in the coming weeks to consolidate the relevance of the degradations observed after irradiation.

Access provided: ASCENT provided samples of 14nm FinFET technology from imec

Ascent Project Ref No

050

User

Peter Schüffelgen

Affiliation

Forschungszentrum Jülich, Germany

Description

Three-dimensional topological insulators (TIs) possess metallic surface states with a spin-locked momentum. In proximity to an s-wave superconductor, Majorana zero modes (MZMs) are predicted to occur at the surface of TIs. Due to their non-abelian exchange statistics, such MZMs are expected to enable fault-tolerant quantum computation.
Within my PhD I am fabricating topological insulator – superconductor hybrid junctions of various geometries. A high quality of the interface between superconductor and topological insulator is crucial. Tyndall’s expertise on Focus Ion Beam and Transmission electron microscopy allowed to actually have a look at such interfaces. In this way I could compare different superconductors and find the best material combination.

Access provided: High Resolution Transmission Electron Microscope (HR-TEM) at Tyndall.

Watch Peter’s story:

Ascent Project Ref No

048

User

Drago Strle

Affiliation

LMFE (Lab. for Microelectronics), Electrical Engineering department, University of Ljubljana, Slovenia

Description

In this work LMFE designed and ASCENT implemented a COMB nano capacitive sensors with 60nm COMB finger thickness and 40nm gaps, using Ti/Al (5nm/50nm) and SiO₂ on top (5nm) in order to improve the sensitivity of our vapor trace detection system. The capacitive sensors were functionalised (at LMFE) with different organic mono-layers, which means that surface adsorption/desorption behaves differently to different molecules in the surrounding gas. Adsorption/desorption of the molecules on the surfaces change the capacitances between the fingers, which we measure using extremely sensitive and low noise, integrated electronic detection system in CMOS technology designed in LMFE. With COMB nano capacitors we have improved the sensitivity approx. 20 times compared to our previous design using MEMS micro capacitors with 1µm gap between the fingers. Measured sensitivity is approx. 20 zF/sqrt(Hz), which leads to the detection limit of approx. 10^-13, or 1 molecule of TNT in 10¹³ molecules of the carrier gas. Sensors with different modifications show different sensitivity to different target molecules, which is a way to improve the selectivity of a vapor trace detection system, using very large array of differently modified sensors with integrated electronics and pattern recognition algorithms based on machine learning concepts.

Access provided: Fabrication of COMB capacitors at Tyndall, with 60nm finger thickness and 40nm gaps, with Ti/Al (5nm/50nm) and SiO₂ on top (5nm).

Ascent Project Ref No

046

User

Dr Elias Aperathitis

Affiliation

Institute of Electronic Structure & Laser (IESL), Foundation for Research & Technology Hellas (FORTH-HELLAS), Heraklion, Crete, Greece

Description

The Microelectronics Research Group (MRG) of IESL/FORTH has pursued research for more than ten years on the development of oxide based materials and devices for applications in the field of transparent optoelectronic devices. One of the major challenges in technology nowadays is the realization of controllable and reliable p-type transparent oxides. Depending on the content of oxygen in Ar plasma highly transparent n-ZnN, n-ZnON and p-ZnON thin films were realised. As a consequence, it is possible to fabricate devices using these materials.

Through ASCENT network, we make use of a High Resolution Transmission Electron Microscopy (HRTEM) facility to investigate and analyse the microstructure and lattice imperfections with depth (depth profiling), the hetero-interfaces and (iii) the long term changes.

Access provided: High Resolution Transmission Electron Microscope (HR-TEM) at Tyndall.

Watch Elias’ story:

Ascent Project Ref No

042

User

Prof Francisco Gámiz

Affiliation

University of Granada, Spain

Description

The project will develop new characterisation and simulation tools required to understand the behaviour of state-of-the-art semiconductor devices. Some effects which were considered so far as second-order effects, are now very important and understanding their behaviour will help to boost the performance of the new devices, not only in the More Moore domain, but also in the More than Moore domain.

Access provided: 300mm CMOS wafer with FDSOI and Si nanowire devices from CEA-Leti.

Ascent Project Ref No

034

User

Asst. Prof Rostislav Rusev

Affiliation

Technical University of Sofia, Bulgaria

Description

The project’s purpose is to fabricate a prototype of an acoustic tweezers using standing surface acoustic waves (SSAW). The aim is to trap and manipulate micro- and nanoparticles, cells, and other biological objects. For this purpose the acoustic tweezers should utilize a wide resonance band of chirped interdigital transducers deposited on the surface of a piezoelectric substrate (IDTs will generate the SAWs). Currently available acoustic tweezers operate in the MHz range. Our tweezer should be deposited on Lithium Niobate (LiNbO3) and to operate in the GHz range. This will enable precise manipulation of smaller objects.

Access provided: Fabrication of devices at Tyndall using e-beam lithography.

Ascent Project Ref No

030

User

Prof Enrique Miranda

Affiliation

Univ. Aut. Barcelona, Spain

Description

This research will explore the electrical stability and failure modes of advanced non-silicon MOS transistors with high-K dielectrics when subjected to electrical stress. The final outcome of degradation is the formation of filamentary pathways spanning the dielectric film between the semiconductor and the metal gate electrode. Depending on the filament location along the channel region and size, the transistor action survives or dies. Understanding under which conditions the devices break down and how they behave after the occurrence of such event are important reliability issues that still need to be investigated in depth for these emerging technologies.

Access provided: Nanoscale test devices and advanced electrical characterisation facilities at Tyndall.

Watch Enrique’s story:

Ascent Project Ref No

029

User

Liang Ye

Affiliation

MESA+, University of Twente, Netherlands

Description

Monolayer doping (MLD) is one alternative doping technique that draws increasing interests in recent years. It offers the benefit of making ultra-shallow doping without causing crystal damage. In this work the tuning of electrical property of silicon nanowires using ultra-shallow doping from MLCD, a variety of MLD, was demonstrated. The electrical properties of the nanowires were investigated in relation to their dimensions (100~200nm in width and height, few hundred nm to few μm in length) and the depth of the doping (10~20nm).

Access provided: Silicon nanowires fabricated at Tyndall.

MIM Diode Cross-section — Cross-section of the MIM diode test structure

Measured IV Characteristics — Measured I-V characteristics

Ascent Project Ref No

023

User

Mircea Dragoman

Affiliation

National Institute for Research and Development in Microtechnologies (IMT), Bucharest, Romania

Description

The Laboratory for micromachined structures, devices and microwave circuits at IMT Bucharest is leading research in the domain of microwave and millimetre-wave devices with potential applications in aerospace, automotive, ambient sensing and energy-harvesting for next generation internet-of-things (IoT). Detection of low-power signals is a very important issue in the field of radar applications, especially at high frequencies (i.e. tens/hundreds of GHz). A potential candidate for such applications is the metal-insulator-metal (MIM) diode, which has the advantage of working at very high cut-off frequencies (up to the THz band) due to a tunnelling effect in the order of some femtoseconds. Thanks to ASCENT Network, we could fabricate at Tyndall on a 4-inch Si wafer (with deep-UV optical lithography) the HfO2-based MIM diodes comprising an 8-nm-thick HfO2 layer. I-V measurements were carried out increasing the top voltage at each step until the device reached the breakdown threshold (around 5.9 V). The devices showed rectifying capabilities and their I-V characteristics are reproducible. The devices were then characterised by using a High Resolution Transmission Electron Microscopy (HRTEM) facility to investigate potential imperfections in the multi-layer stratification (depth profiling).

Access provided: Fabrication of MIM devices at Tyndall. Followed by characterisation (both physical -High Resolution Transmission Electron Microscope- and electrical at radio frequencies).

Ascent Project Ref No

011

User

Prof. Gerard Ghibaudo

Affiliation

IMEP Grenoble, France

Description

This project applied LFN and matching methods developed for FDSOI on FinFETs to gain a better understanding of limiting mechanisms in short channel devices as obtained from statistical measurements. The interface and gate dielectric quality of FinFET was benchmarked with respect to FDSOI previous studies. Assessment of local and global variability of FinFET technology and comparison to FDSOI 14/28nm technologies.

Access provided: 300mm CMOS wafer with FinFET devices and access to characterisation facilities at imec.

Ascent Project Ref No

010

User

Francisco Gámiz / Carlos Márquez

Affiliation

University of Granada, Spain

Description

Two-Dimensional materials have been risen as a complement to the silicon technology to overcome the constraints in the miniaturization of the transistors. Some of the most interesting materials are graphene and its counterparts. In this context, the laboratory of Nanoelectronics, University of Granada, has chemically synthesised one of the graphene compounds, the reduced Graphene Oxide (rGO). Reduced graphene oxide holds exceptional properties such as high electric mobility, flexibility and transparency depending on the concentration. Moreover, assisted laser reduction permits patterning structures with conductive (rGO) and non-conductive (GO) areas in a fast, reliable and cheap way. The deposition of different metals on the surface of rGO samples and the subsequent electrical characterisation would allow the determination of intrinsic conductive parameters such as sheet resistance or contact resistance. Moreover, in-depth reliability analysis such as low frequency characterisation or interface traps determination can be addressed.
Thanks to Ascent Project and the Tyndall National Institute capabilities, three different Reduced Graphene Oxide samples have been successfully metallised with three different metals following photolithography and lift-off standard processes which allowed to pattern TLM structures. Experimental electrical characterisation and reliability issues have been addressed on these samples and the results will be published to improve the knowledge in these new 2D materials.

Access provided: Deposition of contact through optical lithography, EBL and Lift-off processes and SEM Microscopy at Tyndall.