Success Stories


TEM ImageHigh Resolution TEMSusana Devesa

Ascent Project Ref No
146
User
Susana Devesa
Affiliation
Physics Department of University of Aveiro and I3N, Aveiro, Portugal

Description
I am working with bismuth and lanthanide-based materials, being my main objective the dielectric characterization of these ceramic materials. However, for a better understanding of the dielectric properties of a material, it is important to know their structural properties. One of these properties is the crystallite size, that can be determined using different models.
The confirmation of the results obtained with the applied models is very important, mainly because in one of the models, the Uniform Deformation Energy Density Model (UDEDM), we used parameters that are approximations since they have not yet been reported for the Bi1.34Fe0.66Nb1.34O6.35 phase.
Thanks to the ASCENT Network, it was possible to obtain TEM and HR-TEM images that allowed the estimation of the distance between adjacent planes in the Miller indexes and the estimation of the crystallite size. In addition to this process, EDX was also performed.

Access provided: High Resolution Transmission Electron Microscope (HR-TEM) at CEA-Leti.



Ascent134_1Ascent134_2Ascent134_3

Ascent Project Ref No
134
User
Jordi Muñoz Gorriz
Affiliation
Departament d’Enginyeria Electrònica
Universitat Autònoma de Barcelona
, Spain

Description
Reliability analysis of thin oxide films for microelectronic devices relies almost exclusively on electrical measurements. The application of ramped or constant voltage stress to MIM and MIS structures generates defects which results in the formation of a short across the insulating layer. If the energy released during this event is high enough, the damage becomes visible as a mark on the top metal electrode of the structure. The set of marks generated in a single device can be mathematically treated as a point pattern. In this work, standard electrical characterization (I-V, TDDB, etc.) was complemented with a statistical analysis of the breakdown spot distribution. We have made use of spatial statistics methods such as intensity plots, pair correlation analysis, distance histograms, etc. Thanks to the ASCENT project we were able to record videos in the infrared spectrum showing the microexplosions associated with the appearance of the spots. This allowed us to investigate not only the location of the failure sites but also their size and generation time. The thermal images provided us valuable information for the development of a finite-element thermal model of the filamentary current path. The devices were fabricated at Tyndall National Institute, Ireland and were characterized at CEA-Leti, France.

Access provided: Infrared characterisation at CEA-Leti.



Compact Trap Model
Small-signal equivalent circuit
CV Graph
Trap-to-Gate Conductance effect on CV characteristics
Andrzej Mazurak
Andrzej Mazurak

Ascent Project Ref No
130
User
Andrzej Mazurak
Affiliation
Warsaw University of Technology, Institute of Microelectronics and Optoelectronics, Poland

Description
The most common approach to characterize interface or border traps in MIS structures is to measure the gate capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics of a fabricated MIS capacitor or transistor over a wide range of frequencies. An extraction method of traps parameters can be based on different models of the MIS structures, taking into account various charge and discharge mechanisms of traps. The models proposed in literature are usually based on a Nicollian-Brews’ equivalent circuit of a MIS capacitor modified by addition of tunnel exchange paths between the traps and the semiconductor bands and eventually tunnel paths between the gate and the substrate conduction and valence bands. However, they do not comprise charge communication between the traps and the gate electrode. Our group developed a model enhanced by including tunnel communication between the gate and the traps. The model enables to assume an arbitrary discrete distribution of trap states over energy and position in the gate stack and thus it is valid for surface, border and bulk traps. The measurement data obtained via ASCENT was used for model validation. One scientific paper and one conference presentation have been submitted. The work on model development will be continued.

Access provided: Measurement data of admittance (C-G-V-(T)) and current-voltage (I-V-(T)) characteristics for sample structures fabricated and measured by CEA-Leti (p-Si MOSFET transistors with TiN/HfO2/SiO2 gate stack).



TEM Cross SectionOlivia Hendricks

Ascent Project Ref No
105
User
Olivia Hendricks
Affiliation
Department of Chemistry and Department of Materials Science and Engineering, Stanford University, Stanford (CA), U.S.A.

Description
Metal-insulator-semiconductor (MIS) junctions are a promising photoelectrochemical cell design that electronically couple a high-quality semiconductor to an efficient water oxidation catalyst. The photovoltage produced by an MIS junction depends on the strength of the built-in field, or Schottky barrier height. For an n-type silicon photoanode, a high work function metal induces a field that sweeps photogenerated holes to the electrolyte interface for water oxidation.
TiO2-IrOx alloys grown by atomic layer deposition are promising Schottky contacts for n-type silicon photoanodes. These alloys possess a high work function, generating photovoltages of over 600 mV. The ASCENT Network allowed us to assess the morphology and uniformity of ALD TiO2-IrOx alloys on silicon using transmission electron microscopy (TEM). While we were able to probe the photoanode structure by many methods, such as X-ray reflectivity and electrochemical impedance spectroscopy, the cross-sectional TEM performed at Tyndall allowed us to directly characterize the structure of the film. These results were included in our latest paper, cited below:
O. Hendricks, R. Tang-Kong, A. S. Babadi, P. C. McIntyre, C. E. D. Chidsey, “Atomic Layer Deposited TiO2-IrOx Alloys Enable Corrosion Resistant Water Oxidation on Silicon at High Photovoltage”,Chemistry of Materials, 2019, 3 (1), pp. 90-100 (DOI: 10.1021/acs.chemmater.8b03092)

Access provided:Remote access to cross-sectional transmission electron microscopy (TEM) at Tyndall.



Simone Iadanzapoly-Si Photonic Crystal

Ascent Project Ref No
104
User
Simone Iadanza
Affiliation
Centre for Advanced Photonics & Process Analysis, Cork Institute of Technology, Cork, Ireland

Description
The aim of my PhD is to develop a new family of low power optical interconnects such as modulators lasers and photo-detectors using photonic crystals patterned on deposited silicon, vertically integrated to the electronic chip without consuming area of the latter.
A 1µm thick layer of silicon dioxide (SiO2) has to be thermally grown on a carrier silicon wafer first. A 220nm thick layer of amorphous silicon using low-pressure chemical vapour deposition (LPCVD) has to be deposited at 580°C. The wafer has to be then annealed in forming gas, which transforms the amorphous silicon into polycrystalline silicon, and then patterned. One of the primary challenges is to develop high quality optical resonators in deposited silicon due to the relatively high surface roughness of polycrystalline silicon (~10nm). CEA-Leti LPCVD and Chemical-Mechanical Polishing capabilities allowed the fabrication of smooth and uniform poly:Si for the development of the high Q optical resonator, with a surface roughness in the sub-nanometre range.

Access provided: LPCVD of a:Si, annealing into poly:Si and CMP processing at CEA-Leti.



Alexei NazarovSiNWs Test Structure

Ascent Project Ref No
103
User
Alexei Nazarov
Affiliation
Lashkaryov Institute of Semiconductor Physics NASU, Kyiv, Ukraine

Description
The department of Functional materials and nanostructures in Lashkaryov Institute of Semiconductor Physics NAS of Ukraine is one of leading department operating in development of plasma-related technologies for annealing of defects and material ordering at low temperatures (up to 200C). Especially this technology is useful for thin-film and nanostructured devices. In frame of the Ascent project we had opportunity to fabricate Si nanowires (NWs) on SiO2-Si wafer in Tyndall and to perform their electrical characterization during one week visit of Tyndall. Plasma treatment was performed in Ukraine. Obtained results have shown possibility of the plasma treatment to diffuse doping impurity from surface to bulk of the silicon NWs at low temperature and decrease of contact resistivity between metal contact and Si NW. Equipment which located in Tyndall characterization Lab allowed us to perform fast and comprehensive electrical characterization of the devices.

Access provided:Electrical characterisation Lab and Silicon Nanowires (SiNWs) test devices at Tyndall.



Aleksandar PajkanovicRF ProbesNetwork Analyser

Ascent Project Ref No
100
User
Aleksandar Pajkanovic
Affiliation
Faculty of Electrical Engineering, University of Banja Luka, Bosnia and Herzegovina
Faculty of Technical Sciences, University of Novi Sad, Serbia

Description
Meander-type inductors are designed and fabricated in silicon and flexible technology to investigate the performance of this topology and the possibilities of its utilization in RF applications. The CMOS inductor is fabricated using a standard 130 nm technology node and characterized on-chip using a measurement set-up including: wafer probe station, various probes and VNA. Among the most important characteristics of ICs are its PVT variations, which stands for process, voltage and temperature. As this inductor is a passive component, the voltage variations are not discussed. The process variations have been characterized, reported and commented within the paper:

Microelectronics Journal

Via ASCENT project, we are granted the possibility to characterize temperature variations of the designed component. In this way, we would complete PVT variation analysis of the designed inductor, thus gaining valuable knowledge required to improve the design phase of such inductors in future. Results have been published within the paper:

15th SMACD Confererence, 2018

Access provided: Remote access to RF probe station with a temperature controllable chuck and VNA at Tyndall.



Mircea Dragoman
Mircea Dragoman
SEM image of MIM diode
SEM image of MIM diode
TEM image of MIM diode
TEM image of MIM diode

Ascent Project Ref No
081
User
Martino Aldrigo / Mircea Dragoman
Affiliation
National Institute for Research and Development in Microtechnologies (IMT), Bucharest, Romania

Description
The Laboratory for micromachined structures, devices and microwave circuits at IMT Bucharest is leading research in the domain of microwave and millimetre-wave devices with potential applications in aerospace, automotive, ambient sensing and energy-harvesting for next generation internet-of-things (IoT). In view of the high data-rate capabilities offered by 5G technologies, a major challenge is the fabrication of efficient antenna-rectifying diode (“rectenna”) systems, able to work in presence of low input power levels (less than -10 dBm) at high frequencies (i.e. 60 GHz and above). The optimal solution that we found was the integration of a hafnium-based metal-insulator-metal (MIM) diode with a gold/platinum bow-tie antenna on standard high-resistivity silicon/silicon dioxide substrate. This device is perfectly CMOS compatible and shows an excellent responsivity of over 5 V/W with a harvested voltage of almost 250 microvolt.

Thanks to ASCENT Network, we could fabricate at Tyndall on a 4-inch Si wafer (with deep-UV optical lithography) the rectennas comprising a 6-nm-thick hafnium-based MIM diode. The devices were then characterised by using a High Resolution Transmission Electron Microscopy (HRTEM) facility to investigate potential imperfections in the multi-layer stratification (depth profiling). Finally, a complete DC and RF characterisation was performed to test the harvesting capabilities at millimetre waves.

Access provided: Fabrication of MIM devices at Tyndall. Followed by characterisation (both physical -High Resolution Transmission Electron Microscope- and electrical at radio frequencies).



Ascent Project Ref No
077
User
Marco Grande
Affiliation
Politecnico di Bari (Technical University of Bari), Italy

Description
The nPEG group at Politecnico di Bari deals with the design and characterization of integrated plasmonic, photonic and microwave devices combined with two-dimensional materials (e.g. graphene) for sensing and telecommunication applications.
We proposed and optimised silicon nitrate based nanobeam cavities obtaining high Q-factor of the order of 100,000 operating at both 1 µm and 1.5 µm. In particular, by engineering the nanobeam, we demonstrated how to fully control the Q-factor in “asymmetric” environments where the cavity is embedded in a low refractive index medium (e.g. liquid or gas).
These results defined a novel experimental platform for the realization of innovative optical cavities for sensing and optical interconnection since silicon nitride is particularly attractive due to its transparency in the visible range (and over 800-1000nm wavelength range) and biocompatibility.
Thanks to ASCENT Network, we could fabricate at Tyndall a full set of silicon nitride based optical nanobeam cavities with subwavelength nanostructures by means of a combination of electron beam lithography and dry etching. The silicon nitride layers were also deposited at Tyndall by means of PECVD. The experimental measurements carried out at CIT confirmed the numerical findings.

Access provided: Fabrication of optical devices at Tyndall by means: thermal oxide + PECVD SiN deposition, laser wafer dicing, EBL patterning, dry etching and SEM characterisation.



Ascent Project Ref No
074
User
Panagiotis Dimitrakis
Affiliation
Institute of Nanoscience & Nanotechnology, Demokritos, Aghia Paraskevi, Greece

Description
ASCENT Network provided the opportunity for a one week visit in LETI Electrical Characterization Laboratory to perform extensive measurements on LETI nanowires.

Dr Dimitrakis had one-day training in the use of Cascade 300mm wafer prober and measurement software. Following, he had the chance to realize full I-V characterization of large number of Silicon nanowire transistors to analyse the mobility statistical variation as well as to perform specific I-V measurements at different temperatures. Due to the completeness and the state-of-the-art equipment offered by the host laboratory at CEA-leti he was able to carry out many different experiments, to apply many different characterization techniques and collect a significant amount of data during his short stay visit. His interaction with the experts in the lab was of special importance in order to develop links for further research collaborations in the near future.

A 300mm wafer with sub 10nm nanowires on Silicon-on-insulator technology was provided for complementary measurements, modeling and research at Demokritos. These devices should also be used for students training.

Access provided: Electrical characterization Lab of CEA-Leti interactions with experts + Nanowires devices.



Ascent Project Ref No
072
User
Giuseppe Alessio Verni
Affiliation
Material Chemistry and Analysis Group, University College Cork, Cork, Ireland

Description
The Materials Chemistry and Analysis Group (MCAG) of UCC, led by Prof. Justin Holmes, is an active and diverse research group which focuses on the development of methods for the synthesis of nanostructured materials and their in-depth characterisation by advanced electron microscopy and surface analysis techniques. Research in the group ranges from nanowire fabrication using top-down/bottom-up routes, to colloidal nanoparticle synthesis.

Through ASCENT network, we made use of the TOF-SIMS facility in CEA-leti to characterise GaN wafers doped using molecular layer doping (MLD). MLD is an alternative doping technique where dopant-containing molecules are bound to the surface of a semiconductor; the semiconductor is then annealed, and the dopant is in-diffused from the surface leading to conformal and damage-free doping.

Access provided: Dopant characterisation at CEA-Leti using TOF-SIMS.



Ascent Project Ref No
059
User
Prof. Alexei Nazarov
Affiliation
Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences, Ukraine

Description
This project applied low-temperature plasma annealing (not more 250°C) to new types of semiconductor MOS devices such as junctionless III-V MISFET which are very sensitive to high-temperature processing.
Testing of interface and border traps in the interface Al2O3/InGaAs, channel electron mobility, source-drain contact resistance and channel resistivity and leakage current through InGaAs/InP heterojunction will be performed before and after low-temperature plasma annealing to extract an optimal regime of the annealing and demonstration of possibilities of the technology.The project will allow to develop a new approach to control of main electrical parameters of such nanoscaled devices.

Access provided: Nanoscale test devices and advanced electrical characterisation facilities at Tyndall.

Watch Alexei’s story:


Ascent Project Ref No
054
User
Laurent Artola
Affiliation
ONERA, France

Description
This goal of the project was to characterise the sensitivity of the 14nm FinFET technology against radiations with the aim to anticipate their use in embedded applications such as drones or nanosatellites. The effects of radiations on basic devices such n-MOS, p-MOS transistors are analysed. Various electrical parameters of these devices (leakage current, threshold voltage …) are measured and analysed to quantify their degradation due to radiations. The irradiation tests are performed at ONERA. The Cobalt60 facility allows for generating ionizing dose effects in devices. I/V measurements were performed on 2 lots of samples before and after irradiations. The first results have shown a strong degradation of the leakage current after an irradiation of about 500krad. This radiation level corresponds to 30 times of the equivalent dose received by the embedded systems in Earth orbit. The degradation trend of the degradation is relevant with the current works in progress on other FinFET technologies/processes. However, several samples of the tested lots were damaged (especially the bonding due to packaging step and/or transport). This has limited the statistic of irradiated samples. Additions samples were fabricated and packaged at IMEC and should be tested at ONERA in the coming weeks to consolidate the relevance of the degradations observed after irradiation.

Access provided: ASCENT provided samples of 14nm FinFET technology from imec



Ascent Project Ref No
050
User
Peter Schüffelgen
Affiliation
Forschungszentrum Jülich, Germany

Description
Three-dimensional topological insulators (TIs) possess metallic surface states with a spin-locked momentum. In proximity to an s-wave superconductor, Majorana zero modes (MZMs) are predicted to occur at the surface of TIs. Due to their non-abelian exchange statistics, such MZMs are expected to enable fault-tolerant quantum computation.
Within my PhD I am fabricating topological insulator – superconductor hybrid junctions of various geometries. A high quality of the interface between superconductor and topological insulator is crucial. Tyndall’s expertise on Focus Ion Beam and Transmission electron microscopy allowed to actually have a look at such interfaces. In this way I could compare different superconductors and find the best material combination.

Access provided: High Resolution Transmission Electron Microscope (HR-TEM) at Tyndall.

Watch Peter’s story:


Ascent Project Ref No
046
User
Dr Elias Aperathitis
Affiliation
Institute of Electronic Structure & Laser (IESL), Foundation for Research & Technology Hellas (FORTH-HELLAS), Heraklion, Crete, Greece

Description
The Microelectronics Research Group (MRG) of IESL/FORTH has pursued research for more than ten years on the development of oxide based materials and devices for applications in the field of transparent optoelectronic devices. One of the major challenges in technology nowadays is the realization of controllable and reliable p-type transparent oxides. Depending on the content of oxygen in Ar plasma highly transparent n-ZnN, n-ZnON and p-ZnON thin films were realised. As a consequence, it is possible to fabricate devices using these materials.

Through ASCENT network, we make use of a High Resolution Transmission Electron Microscopy (HRTEM) facility to investigate and analyse the microstructure and lattice imperfections with depth (depth profiling), the hetero-interfaces and (iii) the long term changes.

Access provided: High Resolution Transmission Electron Microscope (HR-TEM) at Tyndall.

Watch Elias’ story:


Ascent Project Ref No
042
User
Prof Francisco Gámiz
Affiliation
University of Granada, Spain

Description
The project will develop new characterization and simulation tools required to understand the behaviour of state-of-the-art semiconductor devices. Some effects which were considered so far as second-order effects, are now very important and understanding their behaviour will help to boost the performance of the new devices, not only in the More Moore domain, but also in the More than Moore domain.

Access provided: 300mm CMOS wafer with FDSOI and Si nanowire devices from CEA-Leti.



Ascent Project Ref No
034
User
Asst. Prof Rostislav Rusev
Affiliation
Technical University of Sofia, Bulgaria

Description
The project’s purpose is to fabricate a prototype of an acoustic tweezers using standing surface acoustic waves (SSAW). The aim is to trap and manipulate micro- and nanoparticles, cells, and other biological objects. For this purpose the acoustic tweezers should utilize a wide resonance band of chirped interdigital transducers deposited on the surface of a piezoelectric substrate (IDTs will generate the SAWs). Currently available acoustic tweezers operate in the MHz range. Our tweezer should be deposited on Lithium Niobate (LiNbO3) and to operate in the GHz range. This will enable precise manipulation of smaller objects.

Access provided: Fabrication of devices at Tyndall using e-beam lithography.



Ascent Project Ref No
030
User
Prof Enrique Miranda
Affiliation
Univ. Aut. Barcelona, Spain

Description
This research will explore the electrical stability and failure modes of advanced non-silicon MOS transistors with high-K dielectrics when subjected to electrical stress. The final outcome of degradation is the formation of filamentary pathways spanning the dielectric film between the semiconductor and the metal gate electrode. Depending on the filament location along the channel region and size, the transistor action survives or dies. Understanding under which conditions the devices break down and how they behave after the occurrence of such event are important reliability issues that still need to be investigated in depth for these emerging technologies.

Access provided: Nanoscale test devices and advanced electrical characterisation facilities at Tyndall.

Watch Enrique’s story:



Ascent Project Ref No
029
User
Liang Ye
Affiliation
MESA+, University of Twente, Netherlands

Description
Monolayer doping (MLD) is one alternative doping technique that draws increasing interests in recent years. It offers the benefit of making ultra-shallow doping without causing crystal damage. In this work the tuning of electrical property of silicon nanowires using ultra-shallow doping from MLCD, a variety of MLD, was demonstrated. The electrical properties of the nanowires were investigated in relation to their dimensions (100~200nm in width and height, few hundred nm to few μm in length) and the depth of the doping (10~20nm).

Access provided: Silicon nanowires fabricated at Tyndall.



MIM Diode Cross-section
Cross-section of the MIM diode test structure
TEM image of the MIM diode
TEM image of the MIM diode
Measured IV Characteristics
Measured I-V characteristics

Ascent Project Ref No
023
User
Mircea Dragoman
Affiliation
National Institute for Research and Development in Microtechnologies (IMT), Bucharest, Romania

Description
The Laboratory for micromachined structures, devices and microwave circuits at IMT Bucharest is leading research in the domain of microwave and millimetre-wave devices with potential applications in aerospace, automotive, ambient sensing and energy-harvesting for next generation internet-of-things (IoT). Detection of low-power signals is a very important issue in the field of radar applications, especially at high frequencies (i.e. tens/hundreds of GHz). A potential candidate for such applications is the metal-insulator-metal (MIM) diode, which has the advantage of working at very high cut-off frequencies (up to the THz band) due to a tunnelling effect in the order of some femtoseconds. Thanks to ASCENT Network, we could fabricate at Tyndall on a 4-inch Si wafer (with deep-UV optical lithography) the HfO2-based MIM diodes comprising an 8-nm-thick HfO2 layer. I-V measurements were carried out increasing the top voltage at each step until the device reached the breakdown threshold (around 5.9 V). The devices showed rectifying capabilities and their I-V characteristics are reproducible. The devices were then characterised by using a High Resolution Transmission Electron Microscopy (HRTEM) facility to investigate potential imperfections in the multi-layer stratification (depth profiling).

Access provided: Fabrication of MIM devices at Tyndall. Followed by characterisation (both physical -High Resolution Transmission Electron Microscope- and electrical at radio frequencies).



Ascent Project Ref No
011
User
Prof. Gerard Ghibaudo
Affiliation
IMEP Grenoble, France

Description
This project applied LFN and matching methods developed for FDSOI on FinFETs to gain a better understanding of limiting mechanisms in short channel devices as obtained from statistical measurements. The interface and gate dielectric quality of FinFET was benchmarked with respect to FDSOI previous studies. Assessment of local and global variability of FinFET technology and comparison to FDSOI 14/28nm technologies.

Access provided: 300mm CMOS wafer with FinFET devices and access to characterisation facilities at imec.