Success Stories


Ascent Project Ref No
046
User
Dr Elias Aperathitis
Affiliation
Institute of Electronic Structure & Laser (IESL), Foundation for Research & Technology Hellas (FORTH-HELLAS), Heraklion, Crete, Greece
Description
The Microelectronics Research Group (MRG) of IESL/FORTH has pursued research for more than ten years on the development of oxide based materials and devices for applications in the field of transparent optoelectronic devices. One of the major challenges in technology nowadays is the realization of controllable and reliable p-type transparent oxides. Depending on the content of oxygen in Ar plasma highly transparent n-ZnN, n-ZnON and p-ZnON thin films were realised. As a consequence, it is possible to fabricate devices using these materials.

Through ASCENT network, we make use of a High Resolution Transmission Electron Microscopy (HRTEM) facility to investigate and analyse the microstructure and lattice imperfections with depth (depth profiling), the hetero-interfaces and (iii) the long term changes.

Access provided: High Resolution Transmission Electron Microscope (HR-TEM) at Tyndall.

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Ascent Project Ref No
059
User
Prof. Alexei Nazarov
Affiliation
Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences, Ukraine
Description
This project applied low-temperature plasma annealing (not more 250°C) to new types of semiconductor MOS devices such as junctionless III-V MISFET which are very sensitive to high-temperature processing.
Testing of interface and border traps in the interface Al2O3/InGaAs, channel electron mobility, source-drain contact resistance and channel resistivity and leakage current through InGaAs/InP heterojunction will be performed before and after low-temperature plasma annealing to extract an optimal regime of the annealing and demonstration of possibilities of the technology.The project will allow to develop a new approach to control of main electrical parameters of such nanoscaled devices.

Access provided: Nanoscale test devices and advanced electrical characterisation facilities at Tyndall.

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Ascent Project Ref No
050
User
Peter Schüffelgen
Affiliation
Forschungszentrum Jülich, Germany
Description
Three-dimensional topological insulators (TIs) possess metallic surface states with a spin-locked momentum. In proximity to an s-wave superconductor, Majorana zero modes (MZMs) are predicted to occur at the surface of TIs. Due to their non-abelian exchange statistics, such MZMs are expected to enable fault-tolerant quantum computation.
Within my PhD I am fabricating topological insulator – superconductor hybrid junctions of various geometries. A high quality of the interface between superconductor and topological insulator is crucial. Tyndall’s expertise on Focus Ion Beam and Transmission electron microscopy allowed to actually have a look at such interfaces. In this way I could compare different superconductors and find the best material combination.

Access provided: High Resolution Transmission Electron Microscope (HR-TEM) at Tyndall.

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Ascent Project Ref No
042
User
Prof Francisco Gámiz
Affiliation
University of Granada, Spain
Description
The project will develop new characterization and simulation tools required to understand the behaviour of state-of-the-art semiconductor devices. Some effects which were considered so far as second-order effects, are now very important and understanding their behaviour will help to boost the performance of the new devices, not only in the More Moore domain, but also in the More than Moore domain.

Access provided: 300mm CMOS wafer with FDSOI and Si nanowire devices from CEA-Leti.



Ascent Project Ref No
034
User
Asst. Prof Rostislav Rusev
Affiliation
Technical University of Sofia, Bulgaria
Description
The project’s purpose is to fabricate a prototype of an acoustic tweezers using standing surface acoustic waves (SSAW). The aim is to trap and manipulate micro- and nanoparticles, cells, and other biological objects. For this purpose the acoustic tweezers should utilize a wide resonance band of chirped interdigital transducers deposited on the surface of a piezoelectric substrate (IDTs will generate the SAWs). Currently available acoustic tweezers operate in the MHz range. Our tweezer should be deposited on Lithium Niobate (LiNbO3) and to operate in the GHz range. This will enable precise manipulation of smaller objects.

Access provided: Fabrication of devices at Tyndall using e-beam lithography.



Ascent Project Ref No
030
User
Prof Enrique Miranda
Affiliation
Univ. Aut. Barcelona, Spain
Description
This research will explore the electrical stability and failure modes of advanced non-silicon MOS transistors with high-K dielectrics when subjected to electrical stress. The final outcome of degradation is the formation of filamentary pathways spanning the dielectric film between the semiconductor and the metal gate electrode. Depending on the filament location along the channel region and size, the transistor action survives or dies. Understanding under which conditions the devices break down and how they behave after the occurrence of such event are important reliability issues that still need to be investigated in depth for these emerging technologies.

Access provided: Nanoscale test devices and advanced electrical characterisation facilities at Tyndall.

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Ascent Project Ref No
029
User
Liang Ye
Affiliation
MESA+, University of Twente, Netherlands
Description
Monolayer doping (MLD) is one alternative doping technique that draws increasing interests in recent years. It offers the benefit of making ultra-shallow doping without causing crystal damage. In this work the tuning of electrical property of silicon nanowires using ultra-shallow doping from MLCD, a variety of MLD, was demonstrated. The electrical properties of the nanowires were investigated in relation to their dimensions (100~200nm in width and height, few hundred nm to few μm in length) and the depth of the doping (10~20nm).

Access provided: Silicon nanowires fabricated at Tyndall.



Ascent Project Ref No
011
User
Prof. Gerard Ghibaudo
Affiliation
IMEP Grenoble, France
Description
This project applied LFN and matching methods developed for FDSOI on FinFETs to gain a better understanding of limiting mechanisms in short channel devices as obtained from statistical measurements. The interface and gate dielectric quality of FinFET was benchmarked with respect to FDSOI previous studies. Assessment of local and global variability of FinFET technology and comparison to FDSOI 14/28nm technologies.

Access provided: 300mm CMOS wafer with FinFET devices and access to characterisation facilities at imec.