Success Stories


Ascent Project Ref No
157
User
Victor Kotlyar
Affiliation
Image Processing Systems Institute, the Russian Academy of Science, Russia

Description
It was planned to fabricate two meta lenses. One converts the polarization of the incident beam from a linear to a second-order polarization vortex and focuses the converted radiation. The second is intended for circular polarized incident light, the metalens converts it into a second-order phase vortex using spiral zone plate inside. A feature of these metalenses is that in the center of the focal spot an area with a reverse flow of intensity is formed. If a nano particle is placed into the such area, then it will experience scattering force from the light field in the opposite direction of the optical axis, that is, in the direction of the light source.
Thin film (115nm) of amorphous silicon (a-Si) was deposited on pyrex at the Tyndall National Institute. To create an e-beam mask and etching mask a ZEP resist was applied to the sample by a spinner. The Raith e-line e-beam system was used to create patterns in ZEP. ICP etching was performed to transfer the pattern into a-Si using SF6/C4F8 gases. Stripping of remained hard-etched ZEP mask was done using a 1165 solvent as well as oxygen asher.
The experimental work on the samples is in process.
The AFM images (with varying magnifications) show the surface of the metal. The diameter of the metal oxide is 30µm, the period of the structure is 220 nm, the relief depth is 115 m. This metalinza has a high numerical aperture and focuses laser light with a wavelength of 532nm into a subwavelength light ring.

Access provided: Remote access was provided to nano-fabrication facilities at Tyndall. In particular: Raith e-line e-beam lithography system, STS ICP etcher, oxygen asher, spinner, surface profiler Dektak.



STEM-EDX Image

Ascent Project Ref No
153
User
Kerim Yilmaz
Affiliation
NanoP, THM University of Applied Sciences, Giessen, Germany

Description
The Nanoelectronics Device Modeling Research Group, led by Prof. Dr. Alexander Klös, focuses on device simulation and compact modeling of different type of transistors.
My PhD research tasks include the development of physics related modeling approaches for nanowire transistor structures, in particular considering three-dimensional effects on the electrical behavior.
I received one quarter of a 300mm wafer from CEA-Leti to perform electrical characterizations with our wafer prober, especially on the narrowest SOI Ω-gate NW FETs with different channel length. Of interest are devices with short-channel characteristics such as DIBL, slope degradation or VT roll-off.
The developed compact model for short and long channel cylindrical gate-all-around (GAA) MOSFETs shows good agreement with TCAD Sentaurus simulation data. The experimental data will allow to calibrate the simulator and to evaluate and prove the accuracy and reliability of the developed compact model.
It is a physics based unified model which provides analytical solution for the potential in the channel and can be used for DG, FinFET and GAA MOSFETs with minor changes in the core model.

Access provided: One quarter of a 300mm wafer from CEA-Leti for electrical characterization of SOI Ω-gate FETs.



Christoforos Theodorou at imec

Ascent Project Ref No
152
User
Christoforos Theodorou
Affiliation
IMEP-LAHC, Grenoble, France

Description
Christoforos Theodorou visited our imec labs in March. This collaboration arose from one of the very first collaboration of imec and IMEP-LAHC in ASCENT, with Professor Gerard Ghibaudo.
Firstly, access to the data collected on the automatic testers was granted. The low frequency noise behaviour for the 14nm bulk finFET technology devices provided by imec was characterised by measuring various figures of merit on the imec test setup for a week. This work, which started with a hands-on session the first day, will now continue at the user's facility, using the silicon provided by imec. For this purpose, 3 wafers will be exchanged, and a series of analytical low frequency noise and random telegraph noise measurements will be performed.
The results of this work supported by ASCENT will allow to benchmark the test setups providing a set of guidelines for noise measurements, as well as to develop accurate finFET compact noise models suitable for circuit simulations.

Access provided: Electrical characterisation of 14nm finFET technology at imec.



STEM-EDX Image

Ascent Project Ref No
150
User
Dr. Lynette Keeney
Affiliation
Tyndall National Institute, University College Cork, Ireland

Description
Multiferroic materials, possessing simultaneous electric and magnetic memory states, have been road-mapped as promising multi-state architectures for data-storage scaling beyond current technologies.
In order to optimise one such material system (Aurivillius phase Bi6TixFeyMnzO18) for future miniaturised data-storage technologies, I recently synthesised multiferroic thin film samples at sub-10 nm dimensions.
However, analysis of thin film composition becomes more difficult at reduced dimensions.
Thanks to the ASCENT Network and the microscopy skills of Dr. Zineb Saghi from CEA-Leti, chemical composition analysis of the ultra-thin Aurivillius phase layers was enabled using high resolution STEM (scanning transmission electron microscopy) and EDX (energy dispersive X-ray analysis). This work demonstrates that Mn and Fe, essential to the multiferroic properties, have successfully been incorporated into the ultra-thin layers.

Access provided: High resolution TEM and STEM with EDX at CEA-Leti.



TEM ImageHigh Resolution TEMSusana Devesa

Ascent Project Ref No
146
User
Susana Devesa
Affiliation
Physics Department of University of Aveiro and I3N, Aveiro, Portugal

Description
I am working with bismuth and lanthanide-based materials, being my main objective the dielectric characterization of these ceramic materials. However, for a better understanding of the dielectric properties of a material, it is important to know their structural properties. One of these properties is the crystallite size, that can be determined using different models.
The confirmation of the results obtained with the applied models is very important, mainly because in one of the models, the Uniform Deformation Energy Density Model (UDEDM), we used parameters that are approximations since they have not yet been reported for the Bi1.34Fe0.66Nb1.34O6.35 phase.
Thanks to the ASCENT Network, it was possible to obtain TEM and HR-TEM images that allowed the estimation of the distance between adjacent planes in the Miller indexes and the estimation of the crystallite size. In addition to this process, EDX was also performed.

Access provided: High Resolution Transmission Electron Microscope (HR-TEM) at CEA-Leti.



imec Cu pillarsimec Cu pillarsimec Cu pillarimec mask designWafer listimec process

Ascent Project Ref No
145
User
Daniel Smallwood
Affiliation
Tyndall National Institute, Cork, Ireland

Description
The main goal of the project was to develop an optimized process for utilising Cu pillars in lieu of through substrate vias (TSVs), or to enable the additive deposition of TSV technology. This method removes the need for deep reactive ion etching (DRIE) of the substrate, where the side walls of DRIE etched TSVs are scalloped and the via cross sections have gradated diameters along their axial length. Electrochemically depositing Cu into TSVs is difficult, as current crowding at the via entrance causes heterogeneous deposition rates, often resulting in a dual pyramidal shape of the deposited material. Conversely, electrochemically depositing Cu into feature holes created by lithographic processing is free from all of the aforementioned problems. Lithographic processing is ideal, as the process can be tuned to create a vertical and non-gradated resist profile along the axial length of the feature holes and additionally, current crowding is a non-issue because the deposition is uniaxial in the z-direction.
The first results comprise SEM micrographs of the diced wafers, which have been investigated for pillar side wall and height profiles, as well surface roughness. The pillar side walls were found to be retrograde, with significant variability in the cross-sectional diameter from substrate contact to pillar apex (ex. 70-97µm). In the case of the Cu pillars being used as interconnects, the electrical resistance (R ∝ A-1) will be increased according to the magnitude of the cross-sectional variance.
The pillar height is variable across the wafer, which is due to a changing current density across the die, as corresponds to a variable local feature density. Images were taken with θ = 68°, which corresponds to an actual pillar height of 124µm. The apex of the pillars is over-plated, indicating the photoresist was spun to ≈124µm. Future plans involve utilizing CMP to remove the over-plated material and/or the retrograde side-walls to improve pillar performance by eliminating undesired short circuits and reducing pillar size for increased integrability, whilst maintaining a constant resistance along the axial length.
Pillar circumferential roughness is low (single-digit µm to nanoscale regime), contrary to the conventionally very rough scalloped profile formed as a result of utilising DRIE for via fabrication.

Access provided: 12×12" wafers with Cu pillars plated at variable diameters and densities. The wafers were stopped at various stages along the process fab for a greater depth of pillar characterisation at imec.



1/f Noise measurements
1/f Noise measurements
HF linearity calculation
HF linearity calculation
HF linearity measurement
HF linearity measurement

Ascent Project Ref No
143
User
Mandar S. Bhoir
Affiliation
Department of Electrical Engineering, Indian Institute of Technology Gandhinagar (IIT GN), India

Description
The project had several objectives:

  1. To investigate the impact of thin BOX and Ground Plane doping on transistor’s non-linearity and on low frequency noise
  2. To model the investigated behaviors of noise and non-linearity on top of existing compact FDSOI model to make them more robust and accurate

For that several kind of measurements were performed and analysed. I/V full set were measured and further using derivative techniques, second and third harmonics performances were calculated and compared to high frequency measurements at ~1 GHz for various back gate voltage conditions.
Low frequency noise measurements were also performed. The contributions of noise due to trapping at front interface and at back interface as well as the correlated mobility noise were discussed.

Access provided: ASCENT provided data of I(V), C(V), high frequency linearity and low frequency noise performed by CEA-Leti on 20nm FDSOI transistors.



Susana at TyndallDielectric Constant vs Frequency

Ascent Project Ref No
137
User
Susana Devesa
Affiliation
Physics Department of University of Aveiro and I3N, Aveiro, Portugal

Description
I am working with bismuth and lanthanide-based ceramics, being my main objective the dielectric characterization of these materials.
Thanks to the ASCENT Network, it was possible to measure the dielectric constant and the dielectric losses in a large microwave frequency range, at two and three different temperatures.
The measurements were performed in eighteen samples, using a dielectric probe, with ε' and ε" extracted using the Keysight Technologies’ software.
These measurements complemented the dielectric characterization of the samples, enabling the determination of the temperature coefficient of resonant frequency, which is a key parameter for dielectric characterization.

Access provided: Remote access to dielectric characterisation at Tyndall.



FIB/TEM Lab

Ascent Project Ref No
136
User
Christian Pinto Gómez
Affiliation
Barcelona Microelectronics Institute (IMB-CNM), CSIC, Spain

Description
Structural characterisation of directed self-assembly of block co-polymners Silicon nanowires (SiNWs)

Access provided: Lamella sample preparation by focussed ion beam (FIB) followed by high-resolution transmission electron microscopy (HR-TEM) at Tyndall.

Watch Christian’s story:


Ascent134_1Ascent134_2Ascent134_3

Ascent Project Ref No
134
User
Jordi Muñoz Gorriz
Affiliation
Departament d’Enginyeria Electrònica
Universitat Autònoma de Barcelona
, Spain

Description
Reliability analysis of thin oxide films for microelectronic devices relies almost exclusively on electrical measurements. The application of ramped or constant voltage stress to MIM and MIS structures generates defects which results in the formation of a short across the insulating layer. If the energy released during this event is high enough, the damage becomes visible as a mark on the top metal electrode of the structure. The set of marks generated in a single device can be mathematically treated as a point pattern. In this work, standard electrical characterization (I-V, TDDB, etc.) was complemented with a statistical analysis of the breakdown spot distribution. We have made use of spatial statistics methods such as intensity plots, pair correlation analysis, distance histograms, etc. Thanks to the ASCENT project we were able to record videos in the infrared spectrum showing the microexplosions associated with the appearance of the spots. This allowed us to investigate not only the location of the failure sites but also their size and generation time. The thermal images provided us valuable information for the development of a finite-element thermal model of the filamentary current path. The devices were fabricated at Tyndall National Institute, Ireland and were characterized at CEA-Leti, France.

Access provided: Infra-red characterisation at CEA-Leti.



FIB/TEM LabPhotoFIB/TEM LabPhoto

Ascent Project Ref No
133
User
Paloma Tejedor
Affiliation
Instituto de Ciencia de Materiales de Madrid (ICMM-CSIC), Madrid, Spain

Description
Research activities at the Laboratory of III-V Semiconductor Materials focus on nanoscale selective area growth by molecular beam epitaxy (MBE) of III-V compounds with high mobility and strong spin-orbit coupling (InAs, InGaAs, InSb, …) for their application in electronic and quantum technologies. Presently, our group is engaged in the development of Si CMOS-compatible processes to grow vertical nanowires for tunnel field effect transistors (VTFETs) and scalable arrays of interconnected qubits based on in-plane grown nanowires for topological quantum computing.
Thanks to the ASCENT Network we have had access to the fabrication by electron beam lithography and selective etching of HfO2 and SiO2-masked Si (111) nanostructured substrates having feature sizes as low as 40nm, where we are studying the effect of mask composition on group III adatom diffusion, the formation of antiphase domains and threading dislocations as well as atomic interdiffusion during the selective nucleation and growth of InGaAs/Si and GaSb/InAs/Si nanowire-based heterojunctions by MBE. Due to the variety of feature sizes and pith dimensions present in the nanotemplates, the number of MBE experiments needed to optimize the nanowire morphology and structure is greatly reduced.

Access provided: Nano-fabrication of two 2" nanostructured HfO2/Si(111) and SiO2/Si(111) wafers at Tyndall.



Compact Trap Model
Small-signal equivalent circuit
CV Graph
Trap-to-Gate Conductance effect on CV characteristics
Andrzej Mazurak
Andrzej Mazurak

Ascent Project Ref No
130
User
Andrzej Mazurak
Affiliation
Warsaw University of Technology, Institute of Microelectronics and Optoelectronics, Poland

Description
The most common approach to characterize interface or border traps in MIS structures is to measure the gate capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics of a fabricated MIS capacitor or transistor over a wide range of frequencies. An extraction method of traps parameters can be based on different models of the MIS structures, taking into account various charge and discharge mechanisms of traps. The models proposed in literature are usually based on a Nicollian-Brews’ equivalent circuit of a MIS capacitor modified by addition of tunnel exchange paths between the traps and the semiconductor bands and eventually tunnel paths between the gate and the substrate conduction and valence bands. However, they do not comprise charge communication between the traps and the gate electrode. Our group developed a model enhanced by including tunnel communication between the gate and the traps. The model enables to assume an arbitrary discrete distribution of trap states over energy and position in the gate stack and thus it is valid for surface, border and bulk traps. The measurement data obtained via ASCENT was used for model validation.
The results have been accepted for an oral presentation at the Insulating Films on Semiconductors 2019 Conference, Cambridge, UK. Two papers were published (DOI:10.1116/1.5060674, DOI:10.1016/j.mee.2019.111011). The work on model development will be continued.

Access provided: Measurement data of admittance (C-G-V-(T)) and current-voltage (I-V-(T)) characteristics for sample structures fabricated and measured by CEA-Leti (p-Si MOSFET transistors with TiN/HfO2/SiO2 gate stack).



Raman map measurements on VO2
Raman map measurements on VO2 patch following the red line
RF measurements (S21 parameter)
RF measurements (S21 parameter) on Shunt device, T=30°C → 80°C → 50°C

Ascent Project Ref No
121
User
Guy Garry / Olga Ishchenko
Affiliation
TE-OX, France

Description
TE-OX aims at manufacturing novel optically controlled microwave switches and related devices (phase shifters and reflect arrays) by integrating VO2 thin films in coplanar lines taking benefit of the Metal-Insulator phase transition (MIT).

TE-OX have designed new architectures in order to decrease the switching-time down to the ns and sub-ns scales by triggering the transition respectively by an electrical field or optical absorption. In both cases one needs to optimize the VO2 thickness and, as a consequence, optimize the geometrical parameters of the coplanar lines.
Therefore, the main goal of the project was to investigate the switching time of thermally induced VO2-based RF switches. The RF-devices fabricated on VO2 thin films of different thicknesses were measured on VNA up to 40GHz at different temperatures (RT to 80°C and back to 50°C). To further gain insights of the VO2 transition in these devices, Raman characterisations and SEM observations were performed.

Access provided: Electrical, physical and optical characterisation (microwave S-parameters measurements up to 40GHz and 80°C, SEM and Raman Spectroscopy) at Tyndall.



Theodoros A. OproglidisTest waferIdVg Characteristics

Ascent Project Ref No
119
User
Theodoros A. Oproglidis
Affiliation
Aristotle University of Thessaloniki, Department of Physics, Thessaloniki, Greece

Description
The goal of this project is to investigate the variability of triple-gate junctionless transistors fabricated in imec, Belgium. ASCENT network provided the opportunity for a week’s visit to measure I-V characteristics from a large number of transistors in order to assess both local (matching pairs) and global variability. For this reason, various device technologies were selected. For the local variability investigation, channel length varies from 28nm to 34nm and for global variability from 26nm to 90nm for different number of fins. The devices’ fin width, fin height and channel doping are fixed and equal to 9nm, 40nm and 1.5×1018 cm-3 respectively.

The first results have confirmed the expected variability challenge for the triple-gate junctionless transistors, mainly due to their ultra-high doped channel. Our previous analytical compact model was formulated in order to be continuous and symmetric (verified using the Gummel Symmetry Test – GST) and is used to extract the ideality factor, threshold voltage, mobility, series resistance and the channel length modulation parameter from the variability measurements. The results following the statistical analysis of the aforementioned variables will be used to assess the sources of variability as well as predict the variability in the device performance.

Access provided: Id-Vg measurements to investigate the variability of nanoscale triple-gate junctionless transistors at imec.



Mandar S. Bhoirimec characterisation lab

Ascent Project Ref No
113
User
Mandar S. Bhoir
Affiliation
Department of Electrical Engineering, Indian Institute of Technology Gandhinagar (IIT GN), Gandhinagar, 382355, India

Description
My PhD research is focused on investigating the challenges and optimization of advanced CMOS devices from Analog/RF perspective. Process induced variability has been one of the challenges in scaled CMOS technologies resulting in performance mismatch and hampering production yield. The goal of this project was to experimentally investigate different variability sources and evaluate their impact in advanced FinFET technologies.

Through ASCENT, I got access to imec’s sub-10nm fin-widths FinFET technology and characterization infrastructure. During my imec visit, I received training on different characterization setups (semi-automatic and manual), essential to carry out extensive measurements for variability analysis. Automatic probers have also been used for measurement. Also, the extensive technical discussions with the researchers at imec were quite helpful. The results so far are interesting and highlight key process induced variability sources. We came up with a research paper based on this work (DOI:10.1109/EDTM.2019.8731200) and are planning follow-up interactions.

Overall, the ASCENT project from proposal to on-site access went on quite smoothly and has positively contributed towards my PhD thesis.

Access provided: Access to imec’s FinFET technology and visit to characterization infrastructure.



TEM Cross SectionOlivia Hendricks

Ascent Project Ref No
105
User
Olivia Hendricks
Affiliation
Department of Chemistry and Department of Materials Science and Engineering, Stanford University, Stanford (CA), U.S.A.

Description
Metal-insulator-semiconductor (MIS) junctions are a promising photoelectrochemical cell design that electronically couple a high-quality semiconductor to an efficient water oxidation catalyst. The photovoltage produced by an MIS junction depends on the strength of the built-in field, or Schottky barrier height. For an n-type silicon photoanode, a high work function metal induces a field that sweeps photogenerated holes to the electrolyte interface for water oxidation.
TiO2-IrOx alloys grown by atomic layer deposition are promising Schottky contacts for n-type silicon photoanodes. These alloys possess a high work function, generating photovoltages of over 600 mV. The ASCENT Network allowed us to assess the morphology and uniformity of ALD TiO2-IrOx alloys on silicon using transmission electron microscopy (TEM). While we were able to probe the photoanode structure by many methods, such as X-ray reflectivity and electrochemical impedance spectroscopy, the cross-sectional TEM performed at Tyndall allowed us to directly characterize the structure of the film. These results were included in our latest paper:
O. Hendricks, R. Tang-Kong, A. S. Babadi, P. C. McIntyre, C. E. D. Chidsey, “Atomic Layer Deposited TiO2-IrOx Alloys Enable Corrosion Resistant Water Oxidation on Silicon at High Photovoltage”, Chemistry of Materials, 2019, 3 (1), pp. 90-100 (DOI:10.1021/acs.chemmater.8b03092)

Access provided: Remote access to cross-sectional transmission electron microscopy (TEM) at Tyndall.



Simone Iadanzapoly-Si Photonic Crystal

Ascent Project Ref No
104
User
Simone Iadanza
Affiliation
Centre for Advanced Photonics & Process Analysis, Cork Institute of Technology, Cork, Ireland

Description
The aim of my PhD is to develop a new family of low power optical interconnects such as modulators lasers and photo-detectors using photonic crystals patterned on deposited silicon, vertically integrated to the electronic chip without consuming area of the latter.
A 1µm thick layer of silicon dioxide (SiO2) has to be thermally grown on a carrier silicon wafer first. A 220nm thick layer of amorphous silicon using low-pressure chemical vapour deposition (LPCVD) has to be deposited at 580°C. The wafer has to be then annealed in forming gas, which transforms the amorphous silicon into polycrystalline silicon, and then patterned. One of the primary challenges is to develop high quality optical resonators in deposited silicon due to the relatively high surface roughness of polycrystalline silicon (~10nm). CEA-Leti LPCVD and Chemical-Mechanical Polishing capabilities allowed the fabrication of smooth and uniform poly:Si for the development of the high Q optical resonator, with a surface roughness in the sub-nanometre range.

Access provided: LPCVD of a:Si, annealing into poly:Si and CMP processing at CEA-Leti.



Alexei NazarovSiNWs Test Structure

Ascent Project Ref No
103
User
Alexei Nazarov
Affiliation
Lashkaryov Institute of Semiconductor Physics NASU, Kyiv, Ukraine

Description
The department of Functional materials and nanostructures in Lashkaryov Institute of Semiconductor Physics NAS of Ukraine is one of leading department operating in development of plasma-related technologies for annealing of defects and material ordering at low temperatures (up to 200C). Especially this technology is useful for thin-film and nanostructured devices. In frame of the Ascent project we had opportunity to fabricate Si nanowires (NWs) on SiO2-Si wafer in Tyndall and to perform their electrical characterization during one week visit of Tyndall. Plasma treatment was performed in Ukraine. Obtained results have shown possibility of the plasma treatment to diffuse doping impurity from surface to bulk of the silicon NWs at low temperature and decrease of contact resistivity between metal contact and Si NW. Equipment which located in Tyndall characterization Lab allowed us to perform fast and comprehensive electrical characterization of the devices.

Access provided:Electrical characterisation Lab and Silicon Nanowires (SiNWs) test devices at Tyndall.



Aleksandar PajkanovicRF ProbesNetwork Analyser

Ascent Project Ref No
100
User
Aleksandar Pajkanovic
Affiliation
Faculty of Electrical Engineering, University of Banja Luka, Bosnia and Herzegovina
Faculty of Technical Sciences, University of Novi Sad, Serbia

Description
Meander-type inductors are designed and fabricated in silicon and flexible technology to investigate the performance of this topology and the possibilities of its utilization in RF applications. The CMOS inductor is fabricated using a standard 130 nm technology node and characterized on-chip using a measurement set-up including: wafer probe station, various probes and VNA. Among the most important characteristics of ICs are its PVT variations, which stands for process, voltage and temperature. As this inductor is a passive component, the voltage variations are not discussed. The process variations have been characterized, reported and commented within the paper:

Microelectronics Journal (DOI:10.1016/j.mejo.2016.07.016)

Via ASCENT project, we were granted the possibility to characterize temperature variations of the designed component. In this way, we would complete PVT variation analysis of the designed inductor, thus gaining valuable knowledge required to improve the design phase of such inductors in future. Results have been published within the paper:

15th SMACD Confererence, 2018 (DOI:10.1109/SMACD.2018.8434918)

Access provided: Remote access to RF probe station with a temperature controllable chuck and VNA at Tyndall.



Cantilever Array Rapid Prototype
Cantilever Array Rapid Prototype
EPFL Team
EPFL Team
Test Chips Handover
Test Chips Handover
Test Chips Wafer
Test Chips Wafer

Ascent Project Ref No
089
User
Luis Guillermo Villanueva / Martin Hegner
Affiliation
Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland

Description
Silicon cantilever arrays for label-free diagnostics. The aim of this project is to generate a new type of silicon cantilever arrays with up to 18 sensors per chip for nanomechanical diagnostic investigations. Increasing from a previous design of 8 to 18 sensors on one chip allows to implement multiple target and reference probes in parallel enabling differential readout and improved statistical analysis. A movable laser source will be utilized to readout the nanometer motion of the end of the single clamped beams. The sensor beams will be oscillated at a higher mode in fluids in the MHz regime. These sensors will be used to measure specific interactions of biological analytes in physiological environments.

Access provided: Nano-fabrication of Si cantilever devices at Tyndall.



Jae Woo LeeNoise characteristics

Ascent Project Ref No
087
User
Jae Woo Lee
Affiliation
Dept. of Electronics & Information Engineering, Korea University Sejong Campus, Sejong, South Korea
ICT Convergence Technology for Health & Safety and Department of Electronics and Information Engineering

Description
Thanks to the support from ASCENT program, I have been collaborated with IMEP-LAHC and CEA-LETI in ASCENT with Professor Gerard Ghibaudo and Dr. Sylvain Barraud for the low frequency noise variability analysis of omega-FET.
Recently, due to the aggressive device scaling down, developing next technology node is faced to extremely difficult conditions such as short channel effects and process variations. One of them, because controlling VT uniformly is hard in down scaled devices, the variability of VT (AVT) has been studied to figure out reliable device performance. Likewise, for the reliable device performance of logic application, the reduction of low frequency noise is necessary. Thus, the study of noise variability is important to develop advanced device technologies. In this study, I’m working on that the LFN variability of GAA FETs with different channel (Si vs. SiGe) to quantify the variability of noise and to understand its origin with statistical analysis.
This study has been reported in The 26th Korean Conference on Semiconductors (TB1-G-7) and been prepared for the SCI journal paper.

Access provided: 300mm Wafer with nanowires of geometries down to ∼10nm supplied by CEA-Leti.



Mircea Dragoman
Mircea Dragoman
SEM image of MIM diode
SEM image of MIM diode
TEM image of MIM diode
TEM image of MIM diode

Ascent Project Ref No
081
User
Martino Aldrigo / Mircea Dragoman
Affiliation
National Institute for Research and Development in Microtechnologies (IMT), Bucharest, Romania

Description
The Laboratory for micromachined structures, devices and microwave circuits at IMT Bucharest is leading research in the domain of microwave and millimetre-wave devices with potential applications in aerospace, automotive, ambient sensing and energy-harvesting for next generation internet-of-things (IoT). In view of the high data-rate capabilities offered by 5G technologies, a major challenge is the fabrication of efficient antenna-rectifying diode (“rectenna”) systems, able to work in presence of low input power levels (less than -10 dBm) at high frequencies (i.e. 60 GHz and above). The optimal solution that we found was the integration of a hafnium-based metal-insulator-metal (MIM) diode with a gold/platinum bow-tie antenna on standard high-resistivity silicon/silicon dioxide substrate. This device is perfectly CMOS compatible and shows an excellent responsivity of over 5 V/W with a harvested voltage of almost 250 microvolt.

Thanks to ASCENT Network, we could fabricate at Tyndall on a 4-inch Si wafer (with deep-UV optical lithography) the rectennas comprising a 6-nm-thick hafnium-based MIM diode. The devices were then characterised by using a High Resolution Transmission Electron Microscopy (HRTEM) facility to investigate potential imperfections in the multi-layer stratification (depth profiling). Finally, a complete DC and RF characterisation was performed to test the harvesting capabilities at millimetre waves.

Access provided: Fabrication of MIM devices at Tyndall. Followed by characterisation (both physical -High Resolution Transmission Electron Microscope- and electrical at radio frequencies).



Ascent Project Ref No
079
User
Michael Schroeter & Paulius Sakalas
Affiliation
Technische Universität Dresden, Germany

Description
The goal of this project was the experimental characterization of RF MOSFETs consisting of measuring the high-frequency behaviour over the circuit application relevant bias range.
Standard DC (transfer and output) characteristics were measured first. Then, S-parameters were measured over a frequency range of 1 to 67 GHz. Compared to similar 28nm CMOS technologies, the S-parameters of the measured samples/mask-set showed insufficient gain (S21) and a relatively high input impedance. Therefore, no further investigations were performed.
A second wafer exchange would have been required on a second set of samples to reach better figures of merit, but this was not pursued.
ASCENT provided an estimation of realistic RF characteristics of advanced MOSFETs and a possible comparison to emerging FET technologies.

Access provided: Access to imec’s RF MOSFET technology and characterization infrastructure.



Ascent Project Ref No
077
User
Marco Grande
Affiliation
Politecnico di Bari (Technical University of Bari), Italy

Description
The nPEG group at Politecnico di Bari deals with the design and characterization of integrated plasmonic, photonic and microwave devices combined with two-dimensional materials (e.g. graphene) for sensing and telecommunication applications.
We proposed and optimised silicon nitrate based nanobeam cavities obtaining high Q-factor of the order of 100,000 operating at both 1 µm and 1.5 µm. In particular, by engineering the nanobeam, we demonstrated how to fully control the Q-factor in “asymmetric” environments where the cavity is embedded in a low refractive index medium (e.g. liquid or gas).
These results defined a novel experimental platform for the realization of innovative optical cavities for sensing and optical interconnection since silicon nitride is particularly attractive due to its transparency in the visible range (and over 800-1000nm wavelength range) and biocompatibility.
Thanks to ASCENT Network, we could fabricate at Tyndall a full set of silicon nitride based optical nanobeam cavities with subwavelength nanostructures by means of a combination of electron beam lithography and dry etching. The silicon nitride layers were also deposited at Tyndall by means of PECVD. The experimental measurements carried out at CIT confirmed the numerical findings.

Access provided: Fabrication of optical devices at Tyndall by means: thermal oxide + PECVD SiN deposition, laser wafer dicing, EBL patterning, dry etching and SEM characterisation.



Ascent Project Ref No
076
User
Montserrat Nafría Maqueda
Affiliation
Universitat Autònoma de Barcelona, Barcelona, Spain

Description
In this project, the Reliability of Electron Devices and Circuits research group at the Electronic Engineering Department of the Universitat Autònoma Barcelona carried out the characterization and modelling of time-dependent variability (TDV) in advanced FDSOI technologies. In particular, Random Telegraph Noise (RTN) was investigated, as a function of the gate and body bias voltages. Its relationship with ageing mechanisms such as Bias Temperature Instabilities (BTI) and Channel Hot Carrier (CHC) degradation were addressed.
To carry out this research, a 300mm wafer with SOI Nanowires with dimensions down to ∼10nm was provided by LETI.
First part of the study was performed and supported by ASCENT and will continue in the framework of a Spanish research project, where compact models suitable for circuit simulations will be developed.

Access provided: 300mm wafer with nanowires provided by CEA-Leti.



Ascent Project Ref No
074
User
Panagiotis Dimitrakis
Affiliation
Institute of Nanoscience & Nanotechnology, Demokritos, Aghia Paraskevi, Greece

Description
ASCENT Network provided the opportunity for a one week visit in LETI Electrical Characterization Laboratory to perform extensive measurements on LETI nanowires.

Dr Dimitrakis had one-day training in the use of Cascade 300mm wafer prober and measurement software. Following, he had the chance to realize full I-V characterization of large number of Silicon nanowire transistors to analyse the mobility statistical variation as well as to perform specific I-V measurements at different temperatures. Due to the completeness and the state-of-the-art equipment offered by the host laboratory at CEA-leti he was able to carry out many different experiments, to apply many different characterization techniques and collect a significant amount of data during his short stay visit. His interaction with the experts in the lab was of special importance in order to develop links for further research collaborations in the near future.

A 300mm wafer with sub 10nm nanowires on Silicon-on-insulator technology was provided for complementary measurements, modeling and research at Demokritos. These devices should also be used for students training.

Access provided: Electrical characterization Lab of CEA-Leti interactions with experts + Nanowires devices.



Ascent Project Ref No
072
User
Giuseppe Alessio Verni
Affiliation
Material Chemistry and Analysis Group, University College Cork, Cork, Ireland

Description
The Materials Chemistry and Analysis Group (MCAG) of UCC, led by Prof. Justin Holmes, is an active and diverse research group which focuses on the development of methods for the synthesis of nanostructured materials and their in-depth characterisation by advanced electron microscopy and surface analysis techniques. Research in the group ranges from nanowire fabrication using top-down/bottom-up routes, to colloidal nanoparticle synthesis.

Through ASCENT network, we made use of the TOF-SIMS facility in CEA-leti to characterise GaN wafers doped using molecular layer doping (MLD). MLD is an alternative doping technique where dopant-containing molecules are bound to the surface of a semiconductor; the semiconductor is then annealed, and the dopant is in-diffused from the surface leading to conformal and damage-free doping.

Access provided: Dopant characterisation at CEA-Leti using TOF-SIMS.



Ascent Project Ref No
070
User
Maart van Druenen
Affiliation
Material Chemistry and Analysis Group, University College Cork, Cork, Ireland

Description
Monolayer doping (MLD) is an alternative doping approach that attaches dopant precursors using surface functionalization, followed by a rapid thermal anneal which drives the dopant into the substrate. Oxide functionalization provides an easier method of attaching inexpensive, non-toxic dopant precursors compared to hydrosilylation, making this approach attractive for industrial applications. The overall aim of the project was to quantify the carbon content in Si wafers doped using a phosphorus oxide-MLD process. SIMS analysis gave an indication of phosphorus doping levels and confirmed carbon levels were higher in the oxide cap compared to the underlying Si substrate, demonstrating the oxide-MLD process results in minimal carbon contamination.
Results were published in: “Functionalization of SiO2 Surfaces for Si Monolayer Doping with Minimal Carbon Contamination.” (DOI:10.1021/acsami.7b16950)

Access provided: SIMS measurements and analysis performed at CEA-Leti.



APT & Leti
Atom-probe tomography in Leti
Needle shaped specimen made with HfSe2 and initial results from the Atom-probe tomography

Ascent Project Ref No
069
User
Gioele Mirabelli
Affiliation
Tyndall National Institute, University College Cork, Cork, Ireland

Description
The objective of the work was to investigate the reactions that take place on the surface of 2D-semiconductors after air exposure. These semiconductors are found in the form MX2, where M is a transition metal (Mo, Hf, W, etc.) and X is a chalcogen (S, Se or Te). The metal reacts with oxygen, and this oxidized species is present on the surface of the sample. The chalcogen does not seem to react with oxygen, but is pushed away from the surface forming “protrusions” on the surface (DOI:10.1063/1.4963290). Information on how the material changes over time can clarify the reason of such behavior and open a way of possible solutions to prevent this. Atomic Probe Tomography can give an insight at a scale that is not possible to obtain otherwise. In particular two characteristics of these protrusions are of interest:

  1. The material composition of the protrusions;
  2. The interface between the protrusion and the oxidised metal;

The results pointed to a highly sensitivity and fragility of these protrusions, which are still subject of further studies.

Access provided: Atomic Probe Tomography (APT) at CEA-Leti.



Ascent Project Ref No
067
User
Carlos Márquez/Prof. Francisco Gámiz
Affiliation
Universidad de Granada, Spain

Description
Thanks to Ascent 067 Project, we have carried out the metallization and processing of MoS2 (a transition metal dichalcogenide) back-gate transistors. Due to the layered van der Waal structure and its thin thickness, this material inside the two-dimensional materials family, presents outstanding properties in terms of electrical mobility, electrostatic control of the channel and indirect to direct bandgap depending on the thickness. Properties which make it suitable for a wide range of electronic, optoelectronics and bio-sensing applications. This thin layered material was synthesized following a scalable chemical vapour deposition process at the Nanoelectronic Laboratory, University of Granada, Spain and then metallized and processed following standard CMOS optical lithography at Tyndall National Institute, Cork, Ireland. Despite the theoretical promising properties, experimental devices do not usually fit with the expected performance. As in other technologies (Si, III-V, nanowires …) grain boundaries, dangling bonds, interface traps and defects play an important role in the actual electrical properties of the electronic devices. However, these phenomena are not entirely understood. Therefore, the aim of this project was to shed light into the instability effects which disrupt the performance of MoS2 transistors through the electrical and structural characterization of devices fabricated and processed following scalable methods.

Access provided: Optical lithography, SEM microscopy and on-wafer electrical characterization equipment have been provided at Tyndall.



Ascent Project Ref No
064
User
Takashi Teranishi
Affiliation
Okayama University, Okayama, Japan

Description
Dielectric properties in ferroelectrics are dominantly determined by the dipole polarization; the polarization due to dipole switching in the ferroelectric domains/polar nano regions (PNRs). The dipole relaxation appears in a few to tens of GHz range, whereas relatively large metal electrode loss suppresses the upper frequency limit for the dielectric measurement in general.
The objective of this project is to determine microwave dielectric constant up to tens of GHz utilizing coplanar transmission line for ferroelectric ceramics. The method has been found to work quite nicely in the extraction of permittivity for dielectric substrates. For high dielectric constant substrates the longer and thinner signal lines produce more accurate results.
Microwave dielectric properties of Sn-loaded (Sr, Ba)Nb2O6 (SSBN) were evaluated. For the SSBN samples, we have not seen a clear increase in permittivity with Sn loading but there is an increase in surface pitting with increase in % Sn. Perhaps the increasing porosity leads to increased charge storage but the Transmission line extraction needs very uniform samples.

Access provided: RF Probe station (50-100 GHz range) and Network Analyser at Tyndall.



Ascent Project Ref No
059
User
Prof. Alexei Nazarov
Affiliation
Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences, Ukraine

Description
This project applied low-temperature plasma annealing (not more 250°C) to new types of semiconductor MOS devices such as junctionless III-V MISFET which are very sensitive to high-temperature processing.
Testing of interface and border traps in the interface Al2O3/InGaAs, channel electron mobility, source-drain contact resistance and channel resistivity and leakage current through InGaAs/InP heterojunction will be performed before and after low-temperature plasma annealing to extract an optimal regime of the annealing and demonstration of possibilities of the technology.The project will allow to develop a new approach to control of main electrical parameters of such nanoscaled devices.

Access provided: Nanoscale test devices and advanced electrical characterisation facilities at Tyndall.

Watch Alexei’s story:


Ascent Project Ref No
055
User
Nobuyuki Takeyasu
Affiliation
Okayama University, Okayama, Japan

Description
It is significant to control the shape of metallic nanostructures in plasmonics. Top-down approaches, such as electron-beam or focused ion beam lithography etc., enable metallic nanopatterning in nanoscale resolution. On the other hand, it is able to self-assemble Ag/Au nanoparticles (NPs) into a two-dimensional (2D) array over >cm2, which is referred to as bottom-up approach. The 2D AgNP array is applicable to surface-enhanced Raman spectroscopy (SERS) as SERS active substrates. In this project, we fabricated 2D double-layered AgNP array with one-by-one deposition. The surface and cross-section of the fabricated AgNP arrays were observed with a SEM/TEM also with FIB for cross-section observation. The SEM observation revealed that the fabricated AgNP array was partially broken although this could be caused by the property of silicon substrate different from glass. Based on the results, we switched to one-step deposition for double-layered AgNP array. Recently, we evaluated the extinction properties of the single-, double-, and triple-layered AgNP arrays, and measured SERS with them.

Access provided: FIB+TEM/SEM (Physical characterisation) and Raman spectroscopy (Optical characterisation) at Tyndall.



Ascent Project Ref No
054
User
Laurent Artola
Affiliation
ONERA, France

Description
This goal of the project was to characterise the sensitivity of the 14nm FinFET technology against radiations with the aim to anticipate their use in embedded applications such as drones or nanosatellites. The effects of radiations on basic devices such n-MOS, p-MOS transistors are analysed. Various electrical parameters of these devices (leakage current, threshold voltage …) are measured and analysed to quantify their degradation due to radiations. The irradiation tests are performed at ONERA. The Cobalt60 facility allows for generating ionizing dose effects in devices. I/V measurements were performed on 2 lots of samples before and after irradiations. The first results have shown a strong degradation of the leakage current after an irradiation of about 500krad. This radiation level corresponds to 30 times of the equivalent dose received by the embedded systems in Earth orbit. The degradation trend of the degradation is relevant with the current works in progress on other FinFET technologies/processes. However, several samples of the tested lots were damaged (especially the bonding due to packaging step and/or transport). This has limited the statistic of irradiated samples. Additions samples were fabricated and packaged at IMEC and should be tested at ONERA in the coming weeks to consolidate the relevance of the degradations observed after irradiation.

Access provided: ASCENT provided samples of 14nm FinFET technology from imec



Ascent Project Ref No
050
User
Peter Schüffelgen
Affiliation
Forschungszentrum Jülich, Germany

Description
Three-dimensional topological insulators (TIs) possess metallic surface states with a spin-locked momentum. In proximity to an s-wave superconductor, Majorana zero modes (MZMs) are predicted to occur at the surface of TIs. Due to their non-abelian exchange statistics, such MZMs are expected to enable fault-tolerant quantum computation.
Within my PhD I am fabricating topological insulator – superconductor hybrid junctions of various geometries. A high quality of the interface between superconductor and topological insulator is crucial. Tyndall’s expertise on Focus Ion Beam and Transmission electron microscopy allowed to actually have a look at such interfaces. In this way I could compare different superconductors and find the best material combination.

Access provided: High Resolution Transmission Electron Microscope (HR-TEM) at Tyndall.

Watch Peter’s story:


Ascent Project Ref No
048
User
Drago Strle
Affiliation
LMFE (Lab. for Microelectronics), Electrical Engineering department, University of Ljubljana, Slovenia

Description
In this work LMFE designed and ASCENT implemented a COMB nano capacitive sensors with 60nm COMB finger thickness and 40nm gaps, using Ti/Al (5nm/50nm) and SiO2 on top (5nm) in order to improve the sensitivity of our vapor trace detection system. The capacitive sensors were functionalized (at LMFE) with different organic mono-layers, which means that surface adsorption/desorption behaves differently to different molecules in the surrounding gas. Adsorption/desorption of the molecules on the surfaces change the capacitances between the fingers, which we measure using extremely sensitive and low noise, integrated electronic detection system in CMOS technology designed in LMFE. With COMB nano capacitors we have improved the sensitivity approx. 20 times compared to our previous design using MEMS micro capacitors with 1µm gap between the fingers. Measured sensitivity is approx. 20 zF/sqrt(Hz), which leads to the detection limit of approx. 10-13, or 1 molecule of TNT in 1013 molecules of the carrier gas. Sensors with different modifications show different sensitivity to different target molecules, which is a way to improve the selectivity of a vapor trace detection system, using very large array of differently modified sensors with integrated electronics and pattern recognition algorithms based on machine learning concepts.

Access provided: Fabrication of COMB capacitors at Tyndall, with 60nm finger thickness and 40nm gaps, with Ti/Al (5nm/50nm) and SiO2 on top (5nm).



Ascent Project Ref No
046
User
Dr Elias Aperathitis
Affiliation
Institute of Electronic Structure & Laser (IESL), Foundation for Research & Technology Hellas (FORTH-HELLAS), Heraklion, Crete, Greece

Description
The Microelectronics Research Group (MRG) of IESL/FORTH has pursued research for more than ten years on the development of oxide based materials and devices for applications in the field of transparent optoelectronic devices. One of the major challenges in technology nowadays is the realization of controllable and reliable p-type transparent oxides. Depending on the content of oxygen in Ar plasma highly transparent n-ZnN, n-ZnON and p-ZnON thin films were realised. As a consequence, it is possible to fabricate devices using these materials.

Through ASCENT network, we make use of a High Resolution Transmission Electron Microscopy (HRTEM) facility to investigate and analyse the microstructure and lattice imperfections with depth (depth profiling), the hetero-interfaces and (iii) the long term changes.

Access provided: High Resolution Transmission Electron Microscope (HR-TEM) at Tyndall.

Watch Elias’ story:


Ascent Project Ref No
042
User
Prof Francisco Gámiz
Affiliation
University of Granada, Spain

Description
The project will develop new characterization and simulation tools required to understand the behaviour of state-of-the-art semiconductor devices. Some effects which were considered so far as second-order effects, are now very important and understanding their behaviour will help to boost the performance of the new devices, not only in the More Moore domain, but also in the More than Moore domain.

Access provided: 300mm CMOS wafer with FDSOI and Si nanowire devices from CEA-Leti.



Ascent Project Ref No
034
User
Asst. Prof Rostislav Rusev
Affiliation
Technical University of Sofia, Bulgaria

Description
The project’s purpose is to fabricate a prototype of an acoustic tweezers using standing surface acoustic waves (SSAW). The aim is to trap and manipulate micro- and nanoparticles, cells, and other biological objects. For this purpose the acoustic tweezers should utilize a wide resonance band of chirped interdigital transducers deposited on the surface of a piezoelectric substrate (IDTs will generate the SAWs). Currently available acoustic tweezers operate in the MHz range. Our tweezer should be deposited on Lithium Niobate (LiNbO3) and to operate in the GHz range. This will enable precise manipulation of smaller objects.

Access provided: Fabrication of devices at Tyndall using e-beam lithography.



Ascent Project Ref No
030
User
Prof Enrique Miranda
Affiliation
Univ. Aut. Barcelona, Spain

Description
This research will explore the electrical stability and failure modes of advanced non-silicon MOS transistors with high-K dielectrics when subjected to electrical stress. The final outcome of degradation is the formation of filamentary pathways spanning the dielectric film between the semiconductor and the metal gate electrode. Depending on the filament location along the channel region and size, the transistor action survives or dies. Understanding under which conditions the devices break down and how they behave after the occurrence of such event are important reliability issues that still need to be investigated in depth for these emerging technologies.

Access provided: Nanoscale test devices and advanced electrical characterisation facilities at Tyndall.

Watch Enrique’s story:



Ascent Project Ref No
029
User
Liang Ye
Affiliation
MESA+, University of Twente, Netherlands

Description
Monolayer doping (MLD) is one alternative doping technique that draws increasing interests in recent years. It offers the benefit of making ultra-shallow doping without causing crystal damage. In this work the tuning of electrical property of silicon nanowires using ultra-shallow doping from MLCD, a variety of MLD, was demonstrated. The electrical properties of the nanowires were investigated in relation to their dimensions (100~200nm in width and height, few hundred nm to few μm in length) and the depth of the doping (10~20nm).

Access provided: Silicon nanowires fabricated at Tyndall.



MIM Diode Cross-section
Cross-section of the MIM diode test structure
TEM image of the MIM diode
TEM image of the MIM diode
Measured IV Characteristics
Measured I-V characteristics

Ascent Project Ref No
023
User
Mircea Dragoman
Affiliation
National Institute for Research and Development in Microtechnologies (IMT), Bucharest, Romania

Description
The Laboratory for micromachined structures, devices and microwave circuits at IMT Bucharest is leading research in the domain of microwave and millimetre-wave devices with potential applications in aerospace, automotive, ambient sensing and energy-harvesting for next generation internet-of-things (IoT). Detection of low-power signals is a very important issue in the field of radar applications, especially at high frequencies (i.e. tens/hundreds of GHz). A potential candidate for such applications is the metal-insulator-metal (MIM) diode, which has the advantage of working at very high cut-off frequencies (up to the THz band) due to a tunnelling effect in the order of some femtoseconds. Thanks to ASCENT Network, we could fabricate at Tyndall on a 4-inch Si wafer (with deep-UV optical lithography) the HfO2-based MIM diodes comprising an 8-nm-thick HfO2 layer. I-V measurements were carried out increasing the top voltage at each step until the device reached the breakdown threshold (around 5.9 V). The devices showed rectifying capabilities and their I-V characteristics are reproducible. The devices were then characterised by using a High Resolution Transmission Electron Microscopy (HRTEM) facility to investigate potential imperfections in the multi-layer stratification (depth profiling).

Access provided: Fabrication of MIM devices at Tyndall. Followed by characterisation (both physical -High Resolution Transmission Electron Microscope- and electrical at radio frequencies).



Ascent Project Ref No
011
User
Prof. Gerard Ghibaudo
Affiliation
IMEP Grenoble, France

Description
This project applied LFN and matching methods developed for FDSOI on FinFETs to gain a better understanding of limiting mechanisms in short channel devices as obtained from statistical measurements. The interface and gate dielectric quality of FinFET was benchmarked with respect to FDSOI previous studies. Assessment of local and global variability of FinFET technology and comparison to FDSOI 14/28nm technologies.

Access provided: 300mm CMOS wafer with FinFET devices and access to characterisation facilities at imec.



Ascent Project Ref No
010
User
Francisco Gámiz / Carlos Márquez
Affiliation
University of Granada, Spain

TEM of Ti/Au TLM metallisation
Electrical characterisation

Description
Two-Dimensional materials have been risen as a complement to the silicon technology to overcome the constraints in the miniaturization of the transistors. Some of the most interesting materials are graphene and its counterparts. In this context, the laboratory of Nanoelectronics, University of Granada, has chemically synthesized one of the graphene compounds, the reduced Graphene Oxide (rGO). Reduced graphene oxide holds exceptional properties such as high electric mobility, flexibility and transparency depending on the concentration. Moreover, assisted laser reduction permits patterning structures with conductive (rGO) and non-conductive (GO) areas in a fast, reliable and cheap way. The deposition of different metals on the surface of rGO samples and the subsequent electrical characterization would allow the determination of intrinsic conductive parameters such as sheet resistance or contact resistance. Moreover, in-depth reliability analysis such as low frequency characterization or interface traps determination can be addressed.
Thanks to Ascent Project and the Tyndall National Institute capabilities, three different Reduced Graphene Oxide samples have been successfully metallized with three different metals following photolithography and lift-off standard processes which allowed to pattern TLM structures. Experimental electrical characterization and reliability issues have been addressed on these samples and the results will be published to improve the knowledge in these new 2D materials.

Access provided: Deposition of contact through optical lithography, EBL and Lift-off processes and SEM Microscopy at Tyndall.