ASCENT White paper
An Exploration of Contamination Types and Contamination Control Techniques Currently used in the Fabrication of Nanoelectronics
Leti-NSP SPICE Model
ASCENT is now offering access to Leti-NSP Model through our Virtual Access
- SPICE Model for 3D MOSFETs
- Model valid for GAA Nanowires (1 up to n-stacked)
- Model valid for all possible section shapes of nanowires (cylindrical, rectangular, double gate, …)
ASCENT is now offering access to micro-bumps and Cu pillars for 3D integration.
For more information, visit imec µ-bump offer
imec is now able to offer semi-additive µ-Bumping or Cu pillar processing for users with previously processed Si CMOS or MEMS wafers.
Additionally we can offer short loop µ-Bump or Cu pillar wafer preparation for specific characterisation activities (e.g. metrology development, Failure Analysis understanding, etc.).
Larger integration projects may be considered on a case by case basis.