imec Offer

Download/Print

Access to Silicon Bulk FinFET Technology

Device Analysis
Electrical Characterization Capabilities
Micro-bump & Cu Pillar
Semi-additive µbump and Cu Pillar Process
Test chips documentation and data (Virtual Access)
  • FinFET and GAA
  • PLANAR
Scientific & technical support

Material for Device Analysis

300mm wafers with Bulk FinFET devices
  • 300mm wafers with Bulk FinFET devices
  • Silicon EPI nFET/pFET CMOS fully integrated vehicle
  • Embedded Si:P / SiGe S/D CMOS fully integrated vehicle
  • Replacement Metal Gate [RMG] with Local Interconnect
  • Single level BEOL metal
300mm wafers with Planar Metal Gate devices (28nm)
  • Silicon nFET/pFET CMOS fully integrated vehicle
  • Implanted S/D junctions
  • Replacement Metal Gate [RMG] with Local Interconnect
  • Single level BEOL metal





Gate and RMG N14 Integrated Vehicle Local Interconnect

  • Digital and Analog/RF existing test chips
  • Complete suite of test structures for Reliability/ESD/Matching/Local Layout effects/…
  • Standard devices up to circuit level [Ring-Oscillators, …]
  • State-of-the-art bulk FinFET device baseline




STD Test-chip Content Testchip Documentation
and Simulation
State-of-the-Art Device

  • SPICE models and model cards for digital
  • SPICE models for Layout effect

Electrical Characterization Capabilities

    Available systems and methods:

    • >500 m2 of test labs, ~25 semiauto/manual 300mm probers
    • Statistical data treatment in JMP
    • Fully automatic 300mm parametric testers
    • Semiautomatic 300mm parametric testers
    • Temperature range for test on wafers 77/10K ⇒ high T
    • Fast Pulse testing, Self-Heating characterization
    • HF tests up to 50 GHz
    • Noise measurements
    • Reliability tests: hot carriers, TDDB, charge pumping, …
    • High power tests (10kV, >100A) on 300mm prober
    • Electrostatic discharge LAB




    Semiauto tester 300mm chuck with T capability Full Auto tester 300mm chuck with T capability RF semiauto 300mm tester


    Semi-additive µ-Bump and Cu Pillar Process


    µ-Bump Specifications    Cu Pillar Specifications
    Rule Description Value[µm] Rule Description Value[µm]
    Øtop Øbottom Ø
    µBump pitch 40 Pillar pitch 100
    µBump diameter 7.5 12.5 Pillar diameter 50
    µBump material Cu/Ni/Sn Cu Pillar material Cu
    Material thickness 5/1/3.5 5 Material Thickness 50



    Module Metrology Capability
    • Wafer level defectivity and classification
    • Highly repeatable bump height measurement
    • Wafer-level topography mapping through process



    Accurate Defect Classification
    Example results from one wafer post-seed etch



    Scientific & technical support

    Whenever necessary and upon request of the User, imec can offer scientific support for in-depth data interpretation.